📄 i2chwint.lis
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; WARNING: The variables below are deprecated
; and have been replaced with Read_BufLO
; and Write_BufLO
;-----------------------------------------------
export pI2CHW_Read_Buf
export _pI2CHW_Read_Buf
export pI2CHW_Write_Buf
export _pI2CHW_Write_Buf
;-----------------------------------------------
; END WARNING
;-----------------------------------------------
area InterruptRAM(RAM, REL, CON)
;-----------------------------------------------
; Variable Allocation
;-----------------------------------------------
0000 _I2CHW_bStatus:
0000 I2CHW_bStatus: blk 1
0001 I2CHW_RsrcStatus:
0001 _I2CHW_RsrcStatus: blk 1
0002 I2CHW_Write_Count:
0002 _I2CHW_Write_Count: blk 1
IF SYSTEM_LARGE_MEMORY_MODEL
export pI2CHW_Write_BufHI
export _pI2CHW_Write_BufHI
0003 pI2CHW_Write_BufHI:
0003 _pI2CHW_Write_BufHI: blk 1
ENDIF
;-----------------------------------------------
; WARNING: The variable below is deprecated
; and has been replaced Write_BufLO
;-----------------------------------------------
0004 pI2CHW_Write_Buf:
0004 _pI2CHW_Write_Buf:
0004 ;-----------------------------------------------
0004 ; END WARNING
0004 ;-----------------------------------------------
0004 pI2CHW_Write_BufLO:
0004 _pI2CHW_Write_BufLO: blk 1
0005
IF I2CHW_READ_FLASH
export pI2CHW_Read_BufHI
export _pI2CHW_Read_BufHI
pI2CHW_Read_BufHI:
_pI2CHW_Read_BufHI: blk 1
ELSE
IF SYSTEM_LARGE_MEMORY_MODEL
export pI2CHW_Read_BufHI
export _pI2CHW_Read_BufHI
0005 pI2CHW_Read_BufHI:
0005 _pI2CHW_Read_BufHI: blk 1
ENDIF
ENDIF
;-----------------------------------------------
; WARNING: The variable below is deprecated
; and has been replaced Read_BufLO
;-----------------------------------------------
0006 pI2CHW_Read_Buf:
0006 _pI2CHW_Read_Buf:
0006 ;-----------------------------------------------
0006 ; END WARNING
0006 ;-----------------------------------------------
0006 pI2CHW_Read_BufLO:
0006 _pI2CHW_Read_BufLO: blk 1
0007
IF I2CHW_READ_FLASH
export I2CHW_Read_CountHI
export _I2CHW_Read_CountHI
I2CHW_Read_CountHI:
_I2CHW_Read_CountHI: blk 1
ENDIF
0007 I2CHW_Read_Count:
0007 _I2CHW_Read_Count: blk 1
0008
0008
IF I2CHW_POLLED_PROCESS
I2CHW_Poll_Status: blk 1 ;internal variable used for polled operation
;bit 0 - Write transaction started begin looking for the STOP state to terminate the transaction
I2C_WRITE_STARTED: equ 0x01
;bit 1 - Undefined
;bit 2 - Undefined
;bit 3 - Undefined
;bit 4 - Undefined
;bit 5 - Undefined
;bit 6 - Undefined
;bit 7 - Undefined
ENDIF
;@PSoC_UserCode_INIT@ (Do not change this line.)
;---------------------------------------------------
; Insert your custom declarations below this banner
;---------------------------------------------------
;------------------------
; Includes
;------------------------
;------------------------
; Constant Definitions
;------------------------
;------------------------
; Variable Allocation
;------------------------
;---------------------------------------------------
; Insert your custom declarations above this banner
;---------------------------------------------------
;@PSoC_UserCode_END@ (Do not change this line.)
AREA UserModules (ROM, REL)
export _I2CHW_ISR
export _I2CHW_Poll
export I2CHW_Poll
;;****************************************************
;; I2C_ISR main entry point from vector 60h
;;
;;****************************************************
IF I2CHW_POLLED_PROCESS
_I2CHW_ISR:
reti ; stub out the ISR if this is going to be a polled function
I2CHW_Poll:
_I2CHW_Poll:
; cases are:
; 1. Stop state after a Master write to this slave
; 2. possible Stop condition COMBINED with a new transaction is not a problem since the Stop will only flag that the
; previous write has been completed. (so just call the I2CA_Process routine for this case and let the process routine take
; care of it.
;case 1
IF ( SYSTEM_LARGE_MEMORY_MODEL )
mov reg[CUR_PP], ( >I2CHW_Poll_Status )
ENDIF
tst [I2CHW_Poll_Status], I2C_WRITE_STARTED
jz NOT_I2C_Write
tst reg[ I2CHW_SCR], I2C_STOP_ST
jz NOT_I2C_Write
;make sure the pushes and pops 'line up' or die horribly
push A
push X
IF SYSTEM_LARGE_MEMORY_MODEL
mov A, reg[ IDX_PP ]
push A
ENDIF
jmp STOPTRAP
NOT_I2C_Write:
tst reg[ I2CHW_SCR], I2C_BYTE_COMPL
jnz I2CHW_Process ;if no other critical eventa are in evidence, process an I2C byte if it's done
ret
I2CHW_Process:
_I2CHW_Process: ;don't need to export user will call I2CA_POLL which will call the I2CA_Process routine if necessary
ELSE
;; STUB for polling function when it's un-defined
0000 I2CHW_Poll:
0000 _I2CHW_Poll:
0000 7F ret
0001
0001
0001 ;;*****************************************************************************************
0001 ;; I2C_MASTER main entry point from vector 60h
0001 ;;*****************************************************************************************
0001
0001 _I2CHW_ISR:
ENDIF
0001 08 push A
0002 10 push X
0003
IF SYSTEM_LARGE_MEMORY_MODEL
0003 5DD3 mov A, reg[ IDX_PP ]
0005 08 push A
ENDIF
0006 Process_REENTRY:
0006
0006 ;******************************************************************************************
0006 ;Before doing anything else check for the presence of a STOP_ST in combination with the
0006 ;STOP Interrupt Enable (STOPIE). If this is what happened set appropriate bits,
0006 ;clear and reset the main I2CHW interrupt to assure that we haven't missed a BYTE_COMPLETE
0006 ;interrupt and exit the interrupt. If a BYTE_COMPLETE interrupt is concurrent with the STOP
0006 ;interrupt the next entry to this interrupt will be immediate and the STOPIE bit will now be
0006 ;cleared. This removes the possibility of trying to process two different events within one
0006 ;interrupt.
0006 ;
0006 ;******************************************************************************************
0006 ; Check the Stop Bit in SCR only if the Stop Interrupt is enabled.
0006
0006 49D610 tst reg[I2CHW_CFG],I2C_STOPIE
0009 A006 jz ByteComplProcess
000B 49D720 tst reg[I2CHW_SCR],I2C_STOP_ST ; Test if the Interrupt is due to Stop Condition
000E ;conditions that must be met here are Slave-en
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