📄 ezi2csint.lst
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362 0063 AMD_CR0: equ 63h ; Analog Modulator Control Register 0 (RW)
363 000F AMD_CR0_AMOD0: equ 0Fh ; MASK: Modulation source for analog column 0
364
365 0064 CMP_GO_EN: equ 64h ; Comparator Bus To Global Out Enable (RW)
366 0080 CMP_GO_EN_GOO5: equ 80h ; MASK: Selected Col 1 signal to GOO5
367 0040 CMP_GO_EN_GOO1: equ 40h ; MASK: Selected Col 1 signal to GOO1
368 0030 CMP_GO_EN_SEL1: equ 30h ; MASK: Column 1 Signal Select
369 0008 CMP_GO_EN_GOO4: equ 08h ; MASK: Selected Col 0 signal to GOO4
370 0004 CMP_GO_EN_GOO0: equ 04h ; MASK: Selected Col 0 signal to GOO0
371 0003 CMP_GO_EN_SEL0: equ 03h ; MASK: Column 0 Signal Select
372
373 0066 AMD_CR1: equ 66h ; Analog Modulator Control Register 1 (RW)
374 000F AMD_CR1_AMOD1: equ 0Fh ; MASK: Modulation ctrl for analog column 1
375
376 0067 ALT_CR0: equ 67h ; Analog Look Up Table (LUT) Register 0 (RW)
377 00F0 ALT_CR0_LUT1: equ 0F0h ; MASK: Look up table 1 selection
378 000F ALT_CR0_LUT0: equ 0Fh ; MASK: Look up table 0 selection
379
380 006B CLK_CR3: equ 6Bh ; Analog Clock Source Control Register 3 (RW)
381 0040 CLK_CR3_SYS1: equ 40h ; MASK: Analog Clock 1 selection
382 0030 CLK_CR3_DIVCLK1: equ 30h ; MASK: Analog Clock 1 divider
383 0004 CLK_CR3_SYS0: equ 04h ; MASK: Analog Clock 0 selection
384 0003 CLK_CR3_DIVCLK0: equ 03h ; MASK: Analog Clock 0 divider
385
386 ;------------------------------------------------
387 ; Global Digital Interconnects
388 ;------------------------------------------------
389
390 00D0 GDI_O_IN: equ 0D0h ; Global Dig Interconnect Odd Inputs Reg (RW)
391 00D1 GDI_E_IN: equ 0D1h ; Global Dig Interconnect Even Inputs Reg (RW)
392 00D2 GDI_O_OU: equ 0D2h ; Global Dig Interconnect Odd Outputs Reg (RW)
393 00D3 GDI_E_OU: equ 0D3h ; Global Dig Interconnect Even Outputs Reg (RW)
394
395 ;------------------------------------------------
396 ; Analog Mux Bus Port Enable Bits
397 ;------------------------------------------------
398 00D8 MUX_CR0: equ 0D8h ; Analog Mux Port 0 Bit Enables Register
399 00D9 MUX_CR1: equ 0D9h ; Analog Mux Port 1 Bit Enables Register
400 00DA MUX_CR2: equ 0DAh ; Analog Mux Port 2 Bit Enables Register
401 00DB MUX_CR3: equ 0DBh ; Analog Mux Port 3 Bit Enables Register
402
403 ;------------------------------------------------
404 ; Clock and System Control Registers
405 ;------------------------------------------------
406
407 00DD OSC_GO_EN: equ 0DDh ; Oscillator to Global Outputs Enable Register (RW)
408 0080 OSC_GO_EN_SLPINT: equ 80h ; Enable Sleep Timer onto GOE[7]
409 0040 OSC_GO_EN_VC3: equ 40h ; Enable VC3 onto GOE[6]
410 0020 OSC_GO_EN_VC2: equ 20h ; Enable VC2 onto GOE[5]
411 0010 OSC_GO_EN_VC1: equ 10h ; Enable VC1 onto GOE[4]
412 0008 OSC_GO_EN_SYSCLKX2: equ 08h ; Enable 2X SysClk onto GOE[3]
413 0004 OSC_GO_EN_SYSCLK: equ 04h ; Enable 1X SysClk onto GOE[2]
414 0002 OSC_GO_EN_CLK24M: equ 02h ; Enable 24 MHz clock onto GOE[1]
415 0001 OSC_GO_EN_CLK32K: equ 01h ; Enable 32 kHz clock onto GOE[0]
416
417 00DE OSC_CR4: equ 0DEh ; Oscillator Control Register 4 (RW)
418 0003 OSC_CR4_VC3SEL: equ 03h ; MASK: System VC3 Clock source
419
420 00DF OSC_CR3: equ 0DFh ; Oscillator Control Register 3 (RW)
421
422 00E0 OSC_CR0: equ 0E0h ; System Oscillator Control Register 0 (RW)
423 0080 OSC_CR0_32K_SELECT: equ 80h ; MASK: Enable/Disable External XTAL Osc
424 0040 OSC_CR0_PLL_MODE: equ 40h ; MASK: Enable/Disable PLL
425 0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
426 0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
427 0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
428 0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
429 0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
430 0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
431 0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
432 0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
433 0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
434 0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
435 0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
436 0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
437 0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
438 0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
439 0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
440
441 00E1 OSC_CR1: equ 0E1h ; System VC1/VC2 Divider Control Register (RW)
442 00F0 OSC_CR1_VC1: equ 0F0h ; MASK: System VC1 24MHz/External Clk divider
443 000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
444
445 00E2 OSC_CR2: equ 0E2h ; Oscillator Control Register 2 (RW)
446 0080 OSC_CR2_PLLGAIN: equ 80h ; MASK: High/Low gain
447 0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
448 0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
449 0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
450
451 00E3 VLT_CR: equ 0E3h ; Voltage Monitor Control Register (RW)
452 0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
453 0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
454 0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
455 0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
456 0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
457 0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
458 0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
459
460 00E4 VLT_CMP: equ 0E4h ; Voltage Monitor Comparators Register (R)
461 0008 VLT_CMP_NOWRITE: equ 08h ; MASK: Vcc below Flash Write level
462 0004 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
463 0002 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
464 0001 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
465
466 00E5 ADC0_TR: equ 0E5h ; ADC Column 0 Trim Register
467 00E6 ADC1_TR: equ 0E6h ; ADC Column 1 Trim Register
468
469 00E8 IMO_TR: equ 0E8h ; Internal Main Oscillator Trim Register (W)
470 00E9 ILO_TR: equ 0E9h ; Internal Low-speed Oscillator Trim (W)
471 00EA BDG_TR: equ 0EAh ; Band Gap Trim Register (W)
472 00EB ECO_TR: equ 0EBh ; External Oscillator Trim Register (W)
473
474 00FA FLS_PR1: equ 0FAh ; Flash Program Register 1 (RW)
475 0003 FLS_PR1_BANK: equ 03h ; MASK: Select Active Flash Bank
476
477 00FD DAC_CR: equ 0FDh ; Analog Mux DAC Control Register
478 0008 DAC_CR_IRANGE: equ 08h ; MASK: Sets the DAC Range low or high
479 0006 DAC_CR_OSCMODE: equ 06h ; MASK: Defines the reset mode for AMux
480 0001 DAC_CR_ENABLE: equ 01h ; MASK: Enable/Disable DAC function
481
482 ;;=============================================================================
483 ;; M8C System Macros
484 ;; These macros should be used when their functions are needed.
485 ;;=============================================================================
486
487 ;----------------------------------------------------
488 ; Swapping Register Banks
489 ;----------------------------------------------------
490 macro M8C_SetBank0
491 and F, ~FLAG_XIO_MASK
492 1E8B endm
493
494 macro M8C_SetBank1
495 or F, FLAG_XIO_MASK
496 1E8B endm
497
498 ;----------------------------------------------------
499 ; Global Interrupt Enable/Disable
500 ;----------------------------------------------------
501 macro M8C_EnableGInt
502 or F, FLAG_GLOBAL_IE
503 1E8B endm
504
505 macro M8C_DisableGInt
506 and F, ~FLAG_GLOBAL_IE
507 1E8B endm
508
509 ;----------------------------------------------------
510 ; Enable/Disable Interrupt Mask
511 ;
512 ; Use the following macros to enable/disable
513 ; bits in the Interrupt mask registers,
514 ; INT_MSK0, INT_MSK1 or INT_MSK3.
515 ;
516 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
517 ; M8C_EnableIntMask INT_MSKN, MASK
518 ;
519 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
520 ; and MASK is the bit set to enable or disable
521 ;----------------------------------------------------
522 ; Disable Interrupt Bit Mask(s)
523 macro M8C_DisableIntMask
524 and reg[@0], ~@1 ; disable specified interrupt enable bit
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