📄 ezi2csint.lst
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36 00C0 FLAG_PGMODE_3: equ 0C0h ; Direct to CUR_PP page, indexed to STK_PP page
37 0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
38 0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
39 0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
40 00C0 FLAG_PGMODE_11b: equ 0C0h ; Same as PGMODE_3
41 0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
42 0008 FLAG_SUPER: equ 08h ; Supervisor Mode
43 0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
44 0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
45 0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
46
47
48 ;;=============================================================================
49 ;; Register Space, Bank 0
50 ;;=============================================================================
51
52 ;------------------------------------------------
53 ; Port Registers
54 ; Note: Also see this address range in Bank 1.
55 ;------------------------------------------------
56 ; Port 0
57 0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
58 0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
59 0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
60 0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
61 ; Port 1
62 0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
63 0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
64 0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
65 0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
66 ; Port 2
67 0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
68 0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
69 000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
70 000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
71 ; Port 3
72 000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
73 000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
74 000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
75 000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
76
77 ;------------------------------------------------
78 ; Digital PSoC(tm) block Registers
79 ; Note: Also see this address range in Bank 1.
80 ;------------------------------------------------
81 ; Digital PSoC block 00, Basic Type B
82 0020 DBB00DR0: equ 20h ; data register 0 (#)
83 0021 DBB00DR1: equ 21h ; data register 1 (W)
84 0022 DBB00DR2: equ 22h ; data register 2 (RW)
85 0023 DBB00CR0: equ 23h ; control & status register 0 (#)
86
87 ; Digital PSoC block 01, Basic Type B
88 0024 DBB01DR0: equ 24h ; data register 0 (#)
89 0025 DBB01DR1: equ 25h ; data register 1 (W)
90 0026 DBB01DR2: equ 26h ; data register 2 (RW)
91 0027 DBB01CR0: equ 27h ; control & status register 0 (#)
92
93 ; Digital PSoC block 02, Communications Type B
94 0028 DCB02DR0: equ 28h ; data register 0 (#)
95 0029 DCB02DR1: equ 29h ; data register 1 (W)
96 002A DCB02DR2: equ 2Ah ; data register 2 (RW)
97 002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
98
99 ; Digital PSoC block 03, Communications Type B
100 002C DCB03DR0: equ 2Ch ; data register 0 (#)
101 002D DCB03DR1: equ 2Dh ; data register 1 (W)
102 002E DCB03DR2: equ 2Eh ; data register 2 (RW)
103 002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
104
105 ;-------------------------------------
106 ; Analog Control Registers
107 ;-------------------------------------
108 0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
109 000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
110 0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
111
112 0061 AMUXCFG: equ 61h ; Analog MUX Configuration
113 0030 AMUXCFG_INTCAP: equ 30h ;
114 000E AMUXCFG_MUXCLK: equ 0Eh ;
115 0001 AMUXCFG_EN: equ 01h ;
116
117 0062 PWM_CR: equ 62h ; Pulse-Width Modulator Control
118 0038 PWM_CR_HIGH: equ 38h ; MASK: PWM high time
119 0006 PWM_CR_LOW: equ 06h ; MASK: PWM low time
120 0001 PWM_CR_EN: equ 01h ; MASK: Enable/Disable PWM function
121
122 0064 CMP_CR0: equ 64h ; Analog Comparator Bus Register (#)
123 0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
124 0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
125 0002 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
126 0001 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
127
128 0066 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
129 0020 CMP_CR1_CLDIS1: equ 20h ; MASK: Column 1 comparator output latch
130 0010 CMP_CR1_CLDIS0: equ 10h ; MASK: Column 0 comparator output latch
131
132 0068 ADC0_CR: equ 68h ; Analog Column 0 Configuration
133 0080 ADC0_CR_CMPST: equ 80h ;
134 0040 ADC0_CR_LOREN: equ 40h ;
135 0020 ADC0_CR_SHEN: equ 20h ;
136 0008 ADC0_CR_CBSRC: equ 08h ;
137 0004 ADC0_CR_ADCM: equ 04h ;
138 0001 ADC0_CR_EN: equ 01h ;
139
140 0069 ADC1_CR: equ 69h ; Analog Column 1 Configuration
141 0080 ADC1_CR_CMPST: equ 80h ;
142 0040 ADC1_CR_LOREN: equ 40h ;
143 0020 ADC1_CR_SHEN: equ 20h ;
144 0008 ADC1_CR_CBSRC: equ 08h ;
145 0004 ADC1_CR_ADCM: equ 04h ;
146 0001 ADC1_CR_EN: equ 01h ;
147
148 ; Continuous Time PSoC block Type E Row 0 Col 0
149 0072 ACE00CR1: equ 72h ; Control register 1 (RW)
150 0073 ACE00CR2: equ 73h ; Control register 2 (RW)
151
152 ; Continuous Time PSoC block Type E Row 0 Col 1
153 0076 ACE01CR1: equ 76h ; Control register 1 (RW)
154 0077 ACE01CR2: equ 77h ; Control register 2 (RW)
155
156 ; Switched Cap PSoC blockType E Row 1 Col 0
157 0080 ASE10CR0: equ 80h ; Control register 0 (RW)
158
159 ; Switched Cap PSoC blockType E Row 1 Col 1
160 0084 ASE11CR0: equ 84h ; Control register 0 (RW)
161
162 ;-----------------------------------------------
163 ; Global General Purpose Data Registers
164 ;-----------------------------------------------
165 006C TMP_DR0: equ 6Ch ; Temporary Data Register 0 (RW)
166 006D TMP_DR1: equ 6Dh ; Temporary Data Register 1 (RW)
167 006E TMP_DR2: equ 6Eh ; Temporary Data Register 2 (RW)
168 006F TMP_DR3: equ 6Fh ; Temporary Data Register 3 (RW)
169
170 ;------------------------------------------------
171 ; Row Digital Interconnects
172 ;
173 ; Note: the following registers are mapped into
174 ; both register bank 0 AND register bank 1.
175 ;------------------------------------------------
176
177 00B0 RDI0RI: equ 0B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
178 00B1 RDI0SYN: equ 0B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
179 00B2 RDI0IS: equ 0B2h ; Row 0 Input Select Register (RW)
180 00B3 RDI0LT0: equ 0B3h ; Row 0 Look Up Table Register 0 (RW)
181 00B4 RDI0LT1: equ 0B4h ; Row 0 Look Up Table Register 1 (RW)
182 00B5 RDI0RO0: equ 0B5h ; Row 0 Output Register 0 (RW)
183 00B6 RDI0RO1: equ 0B6h ; Row 0 Output Register 1 (RW)
184
185 ;-----------------------------------------------
186 ; Ram Page Pointers
187 ;-----------------------------------------------
188 00D0 CUR_PP: equ 0D0h ; Current Page Pointer
189 00D1 STK_PP: equ 0D1h ; Stack Page Pointer
190 00D3 IDX_PP: equ 0D3h ; Index Page Pointer
191 00D4 MVR_PP: equ 0D4h ; MVI Read Page Pointer
192 00D5 MVW_PP: equ 0D5h ; MVI Write Page Pointer
193
194 ;------------------------------------------------
195 ; I2C Configuration Registers
196 ;------------------------------------------------
197 00D6 I2C_CFG: equ 0D6h ; I2C Configuration Register (RW)
198 0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
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