📄 ezi2csint.lst
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HI-TECH Software Macro Assembler (PSoC MCU) V9.61PL1
Mon Dec 22 13:58:01 2008
1 ;;*****************************************************************************
2 ;;*****************************************************************************
3 ;; FILENAME: EzI2Cs.inc
4 ;; Version: 1.1, Updated on 2008/9/17 at 16:14:40
5 ;; Generated by PSoC Designer ???
6 ;;
7 ;; DESCRIPTION: Assembler declarations for the EzI2Cs user module for the
8 ;; 29/27/24/22xxx PSoC family of devices
9 ;;-----------------------------------------------------------------------------
10 ;; Copyright (c) Cypress MicroSystems 2004. All Rights Reserved.
11 ;;*****************************************************************************
12 ;;*****************************************************************************
13
14
15 ;--------------------------------------------------
16 ; Constants for EzI2Cs API's.
17 ;--------------------------------------------------
18 0001 EzI2Cs_DYNAMIC_ADDR: equ 1
19 0001 EzI2Cs_ROM_ENABLE: equ 1
20 0000 EzI2Cs_SYNC_FIX: equ 0
21
22 IF (EzI2Cs_ROM_ENABLE)
23 007E EzI2Cs_ADDR_MASK: equ 0x7E ; Mask off ROM Addr and R/W bit
24 ELSE
25 EzI2Cs_ADDR_MASK: equ 0xFE ; Mask off R/W bit
26 ENDIF
27
28 ;; I2C_CFG Register definitions
29 0040 EzI2Cs_CFG_PSelect: equ 0x40 ; Pin Select, 0 = P1,7/5, 1 = P1,1,0
30 0020 EzI2Cs_CFG_BUS_ERROR_IE: equ 0x20 ; Enable Interrupt on bus error
31 0010 EzI2Cs_CFG_STOP_IE: equ 0x10 ; Enable Interrupt on Stop condition
32 0000 EzI2Cs_CFG_CLOCK_100K: equ 0x00 ; 100kHz Standard clock rate
33 0004 EzI2Cs_CFG_CLOCK_400K: equ 0x04 ; 400kHz Fast Mode
34 0008 EzI2Cs_CFG_CLOCK_50K: equ 0x08 ; 50kHz Standard Mode
35 0002 EzI2Cs_CFG_Master_EN: equ 0x02 ; Enable Master Mode.
36 0001 EzI2Cs_CFG_Slave_EN: equ 0x01 ; Enable Slave Mode.
37
38 ;; I2C_SCR Register definitions
39 0080 EzI2Cs_SCR_BUS_ERROR: equ 0x80 ; Bus Error
40 0040 EzI2Cs_SCR_LOST_ARB: equ 0x40 ; Lost Arbitration (Master Only)
41 0020 EzI2Cs_SCR_STOP_STATUS: equ 0x20 ; Stop Status
42 0010 EzI2Cs_SCR_ACK: equ 0x10 ; ACK Status
43 0000 EzI2Cs_SCR_NAK: equ 0x00 ; NAK Status
44 0008 EzI2Cs_SCR_ADDRESS: equ 0x08 ; Data is address.
45 0004 EzI2Cs_SCR_TRANSMIT: equ 0x04 ; Sets direction of data flow
46 0002 EzI2Cs_SCR_LRB: equ 0x02 ; Last Received Bit
47 0001 EzI2Cs_SCR_BYTE_COM: equ 0x01 ; Byte Complete
48
49 ;; I2C_DR Register definitions (Data Register)
50
51 ;; I2C_MSCR Register definitions (Master Mode Only)
52 0008 EzI2Cs_MSCR_BUS_BUSY: equ 0x08 ; Bus is Busy with other trafic
53 0004 EzI2Cs_MSCR_MASTER_MODE: equ 0x04 ; ?????
54 0002 EzI2Cs_MSCR_RESTART_REN: equ 0x02 ; Generate a Restart
55 0001 EzI2Cs_MSCR_START_REN: equ 0x01 ; Generate a Start
56
57
58 ;; Valid address
59 0090 EzI2Cs_SLAVE_ADDR: equ (0x48<<1) ; Permanent Slave Address
60 0080 EzI2Cs_ALT_SLAVE_ADDR: equ ((0x48<<1)&0x80) ; Permanent Slave Address
61
62 0080 EzI2Cs_ALT_ADDR_BIT: equ 0x80 ; Alternate Address bit
63 0001 EzI2Cs_RW_FLAG: equ 0x01 ; Read/Write flag
64 0001 EzI2Cs_RD_FLAG: equ 0x01 ; Read/Write flag
65 0000 EzI2Cs_WR_FLAG: equ 0x00 ; Read/Write flag
66
67 00D6 EzI2Cs_CFG_REG: equ d6h ; I2C Configuration Register
68 00D7 EzI2Cs_SCR_REG: equ d7h ; I2C Enable Master/Slave Block Operation
69 00D8 EzI2Cs_DR_REG: equ d8h ; I2C Status and Control Register
70 00D9 EzI2Cs_MSCR_REG: equ d9h ; I2C Master Status and Control
71
72
73 ;; Bit definitions for EzI2Cs_bState
74 00B0 EzI2Cs_ACTIVITY_MASK: equ 0xB0 ; Activity Mask
75 0080 EzI2Cs_ANY_ACTIVITY: equ 0x80 ; Any I2C bus activity.
76 0020 EzI2Cs_READ_ACTIVITY: equ 0x20 ; I2C read activity at primary address.
77 0010 EzI2Cs_WRITE_ACTIVITY: equ 0x10 ; I2C write activity at primary address.
78
79 ;--------------------------------------------------
80 ; EzI2Cs API Constants
81 ;--------------------------------------------------
82
83 00DE EzI2Cs_INT_REG: equ 0x0de
84 0001 EzI2Cs_INT_MASK: equ 0x01
85
86
87 ;I2C_(status and control) reg write macro
88 ;----------------------------------------------------
89 ; I2C_SCR and I2C_MSCR reg write macro
90 ;
91 ; Use the following macros to write to the I2C_SCR register
92 ; Usage: SetI2C_SCR WRITE_VALUE
93 ;
94 ; where WRITE_VALUE is the data to be writen
95 ;
96 ;----------------------------------------------------
97
98
99 ; Write to the EzI2Cs_SCR register
100 macro SetEzI2Cs_SCR
101 IF (EzI2Cs_SYNC_FIX)
102 or F, FLAG_XIO_MASK ; set bank1
103 push X
104 mov X, A ; if data for I2C_SCR was in A save it in X
105 mov A, reg[OSC_CR0] ;
106 push A
107 and A, ~0x07 ; Mask off CPU speed
108 or A, 0x01 ; Set CPU to 6 MHz
109 mov reg[OSC_CR0], A ;
110 and F, ~FLAG_XIO_MASK ; set bank0
111 mov A, X ; if the operation uses data in A get it out of X
112 mov reg[EzI2Cs_SCR_REG], @0 ; write data to reg[I2C_SCR]
113 or F, FLAG_XIO_MASK ; set bank1
114 pop A ; restore original clock speed
115 mov reg[OSC_CR0], A
116 and F, ~FLAG_XIO_MASK ; set bank0
117 mov A, X ; if A was data restore it from X now
118 pop X ; restore original accumulator
119 ELSE
120 mov reg[EzI2Cs_SCR_REG], @0 ; write data to reg[I2C_SCR]
121 ENDIF
122 1E8B endm
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8C.INC -- M8C21030 Microcontroller Device System Declarations
4 ;;;
5 ;;; Copyright (c) 2005 Cypress MicroSystems, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides address constants, bit field masks and a set of macro
9 ;;; facilities for the Cypress MicroSystems 21x3x Microcontroller devices.
10 ;;;
11 ;;; Last Modified: January 21, 2005
12 ;;;
13 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
15 ;;=============================================================================
16 ;; Definition of abbreviations used in the descriptions below
17 ;; (RW) The register or bit supports reads and writes
18 ;; (W) The register or bit is write-only
19 ;; (R) The register or bit is read-only
20 ;; (#) Access to the register is bit specific (see the family datasheet)
21 ;; (RC) The register or bit can be read, but writing a 0 will clear it,
22 ;; writing a 1 will have no effect.
23 ;;=============================================================================
24
25 ;;=============================================================================
26 ;; System Registers
27 ;;=============================================================================
28
29 ;----------------------------
30 ; Flag Register Bit Fields
31 ;----------------------------
32 00C0 FLAG_PGMODE_MASK: equ 0C0h ; Paging control for > 256 bytes of RAM
33 0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
34 0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
35 0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
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