📄 i2chwcommon.lis
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0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro RAM_EPILOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro REG_PRESERVE( IOReg )
0000 mov A, reg[ @IOReg ]
0000 push A
0000 macro REG_RESTORE( IOReg )
0000 pop A
0000 mov reg[ @IOReg ], A
0000 macro ISR_PRESERVE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_RESTORE MVW_PP
0000 REG_RESTORE MVR_PP
0000 REG_RESTORE IDX_PP
0000 REG_RESTORE CUR_PP
0000 ENDIF
00DE I2CHW_INT_REG: equ 0x0de
0001 I2CHW_INT_MASK: equ 0x01
0000
0000
0000
0000 ;-----------------
0000 ; Misc. equates
0000 ;-----------------
0000
0000 ;I2CHW_RsrcStatus byte, Status Bit definitions
0001 I2CHW_RD_NOERR: equ 0x1 ;read completed without errors
0002 I2CHW_RD_OVERFLOW: equ 0x2 ;master read more bytes than were contained in read buffer
0004 I2CHW_RD_COMPLETE: equ 0x4 ;last read transaction complete
0008 I2CHW_READFLASH: equ 0x8 ;set- next read will use flash read buffer, clear- next read will use ram read buffer
0010 I2CHW_WR_NOERR: equ 0x10 ;write completed without errors
0020 I2CHW_WR_OVERFLOW: equ 0x20 ;received bytes exceeded write buffer length
0040 I2CHW_WR_COMPLETE: equ 0x40 ;Master uses this definition, slave uses that below.
0040 I2CHW_ISR_NEW_ADDR: equ 0x40 ;New addre received (can infer that previous transaction is complete)
0080 I2CHW_ISR_ACTIVE: equ 0x80 ;ISR for I2C_slave is is active
0000
0000
0004 fI2C_NAKnextWr: equ 0x04 ;flag to tell slave to nak next byte from master
0000
0000
0000 ;=== I2C equates ===
0000
0000
0000
00D7 I2CHW_SCR: equ d7h;: equ 0xd7 ;Slave SCR register location bank 0
0000
0080 I2CM_BUSERR: equ 0x80
0040 I2CM_LOSTARB: equ 0x40
0020 I2C_STOP_ST: equ 0x20
0010 I2C_ACKOUT: equ 0x10
0008 I2C_ADDRIN: equ 0x08
0004 I2C_TX: equ 0x04 ;compliment is RX
0002 I2C_LST_BIT: equ 0x02
0001 I2C_BYTE_COMPL: equ 0x01
0000
00D6 I2CHW_CFG: equ d6h;: equ 0xd6 ;I2C CFG register location bank 0
0000
0020 I2C_BUSERRIE: equ 0x20
0010 I2C_STOPIE: equ 0x10
0008 I2C_CLKR1: equ 0x08
0004 I2C_CLKR0: equ 0x04
0002 I2C_M_EN: equ 0x02
0001 I2C_S_EN: equ 0x01
0000
00D9 I2CHW_MSCR: equ d9h;: equ 0xd9 ;Master SCR register location bank 0
0000
0008 I2CM_BUSBUSY: equ 0x08
0004 I2CM_MASTEROP: equ 0x04
0002 I2CM_RESTRT: equ 0x02
0001 I2CM_SNDSTRT: equ 0x01
0000
00D8 I2CHW_DR: equ d8h;: equ 0xd8 ;I2C DATA register location bank 0
0000
0000
0000 ;Equates used as conditional compile keys
0000
0000
0000 I2CHW_READ_BUFTYPE: equ 0x0
0000
0000 I2CHW_READ_FLASH: equ I2CHW_READ_BUFTYPE & 0x01
0000
0000 I2CHW_24MHZ_FIX: equ 0x0
0000
0000 I2CHW_THROTTLE_CLK_RATE: equ I2CHW_24MHZ_FIX & 0x01
0000
0000 I2CHW_POLLING_ENABLE: equ 0x0
0000
0000 I2CHW_POLLED_PROCESS: equ I2CHW_POLLING_ENABLE & 0x01
0000
0000 ;I2C_(status and control) reg write macro
0000 ;----------------------------------------------------
0000 ; I2C_SCR and I2C_MSCR reg write macro
0000 ;
0000 ; Use the following macros to write to the I2C_SCR register
0000 ; Usage: SetI2C_MSCR WRITE_VALUE
0000 ; SetI2C_SCR WRITE_VALUE
0000 ; SetI2C_CFG WRITE_VALUE
0000 ;
0000 ; where WRITE_VALUE is the data to be writen
0000 ;
0000 ;----------------------------------------------------
0000 ; Write to the I2CHW_SCR register
0000 ;
0000 macro SetI2CHW_SCR
0000
0000 IF I2CHW_THROTTLE_CLK_RATE
0000 or F, FLAG_XIO_MASK ; set bank1
0000 push X
0000 mov X, A ; if data for I2C_SCR was in A save it in X
0000 mov A, reg[OSC_CR0] ;
0000 push A
0000 and A, ~0x07
0000 or A, 0x1
0000 mov reg[OSC_CR0], A ; throttle the clock down to 6Mhz
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 mov A, X ; if the operation uses data in A get it out of X
0000 mov reg[0xD7], @0 ; write data to reg[I2C_SCR]
0000 or F, FLAG_XIO_MASK ; set bank1
0000 pop A ; restore original clock speed
0000 mov reg[OSC_CR0], A
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 mov A, X ; if A was data restore it from X now
0000 pop X ; restore original accumulator
0000 ELSE
0000 mov reg[0xD7], @0 ; write data to reg[I2C_SCR]
0000 ENDIF
0000 macro SetI2CHW_MSCR
0000
0000 IF I2CHW_THROTTLE_CLK_RATE
0000 or F, FLAG_XIO_MASK ; set bank1
0000 push X
0000 mov X, A ; if data for I2C_SCR was in A save it in X
0000 mov A, reg[OSC_CR0] ;
0000 push A
0000 and A, ~0x07
0000 or A, 0x01
0000 mov reg[OSC_CR0], A ; throttle the clock down to 6Mhz
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 mov A, X ; if the operation uses data in A get it out of X
0000 mov reg[0xD9], @0 ; write data to reg[I2C_MSCR]
0000 or F, FLAG_XIO_MASK ; set bank1
0000 pop A ; restore original clock speed
0000 mov reg[OSC_CR0], A
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 mov A, X ; if A was data restore it from X now
0000 pop X ; restore original accumulator
0000 ELSE
0000 mov reg[0xD9], @0 ; write data to reg[I2C_MSCR]
0000 ENDIF
0000 macro BitSetI2CHW_CFG
0000
0000 IF I2CHW_THROTTLE_CLK_RATE
0000 or F, FLAG_XIO_MASK ; set bank1
0000 push A
0000 mov A, reg[OSC_CR0] ;
0000 push A
0000 and A, ~0x07
0000 or A, 0x02
0000 mov reg[OSC_CR0], A ; throttle the clock down to 12Mhz
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 or reg[0xD6], @0 ; write data to reg[I2C_CFG]
0000 or F, FLAG_XIO_MASK ; set bank1
0000 pop A ; restore original clock speed
0000 mov reg[OSC_CR0], A
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 pop A ; restore original accumulator
0000 ELSE
0000 or reg[0xD6], @0 ; write data to reg[I2C_CFG]
0000 ENDIF
0000 macro BitClrI2CHW_CFG
0000
0000 IF I2CHW_THROTTLE_CLK_RATE
0000 or F, FLAG_XIO_MASK ; set bank1
0000 push A
0000 mov A, reg[OSC_CR0] ;
0000 push A
0000 and A, ~0x07
0000 or A, 0x02
0000 mov reg[OSC_CR0], A ; throttle the clock down to 12Mhz
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 and reg[0xD6], ~@0 ; write data to reg[I2C_CFG]
0000 or F, FLAG_XIO_MASK ; set bank1
0000 pop A ; restore original clock speed
0000 mov reg[OSC_CR0], A
0000 and F, ~FLAG_XIO_MASK ; set bank0
0000 pop A ; restore original accumulator
0000 ELSE
0000 and reg[0xD6], ~@0 ; write data to reg[I2C_CFG]
0000 ENDIF
0000 macro I2CHW_SERVICE_RETURN
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