📄 psocconfigtbl.lis
字号:
0000
00E1 OSC_CR1: equ 0E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ 0F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ 0E2h ; Oscillator Control Register 2 (RW)
0080 OSC_CR2_PLLGAIN: equ 80h ; MASK: High/Low gain
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ 0E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000
00E4 VLT_CMP: equ 0E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_NOWRITE: equ 08h ; MASK: Vcc below Flash Write level
0004 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
0002 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
0001 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
0000
00E5 ADC0_TR: equ 0E5h ; ADC Column 0 Trim Register
00E6 ADC1_TR: equ 0E6h ; ADC Column 1 Trim Register
0000
00E8 IMO_TR: equ 0E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ 0E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ 0EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ 0EBh ; External Oscillator Trim Register (W)
0000
00FA FLS_PR1: equ 0FAh ; Flash Program Register 1 (RW)
0003 FLS_PR1_BANK: equ 03h ; MASK: Select Active Flash Bank
0000
00FD DAC_CR: equ 0FDh ; Analog Mux DAC Control Register
0008 DAC_CR_IRANGE: equ 08h ; MASK: Sets the DAC Range low or high
0006 DAC_CR_OSCMODE: equ 06h ; MASK: Defines the reset mode for AMux
0001 DAC_CR_ENABLE: equ 01h ; MASK: Enable/Disable DAC function
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
export LoadConfigTBL_hbtouchkey_Bank1
export LoadConfigTBL_hbtouchkey_Bank0
export LoadConfigTBL_hbtouchkey_Ordered
export UnloadConfigTBL_hbtouchkey_Bank1
export UnloadConfigTBL_hbtouchkey_Bank0
export ReloadConfigTBL_hbtouchkey_Bank1
export ReloadConfigTBL_hbtouchkey_Bank0
export LoadConfigTBL_Config1_Bank1
export LoadConfigTBL_Config1_Bank0
export UnloadConfigTBL_Config1_Bank1
export UnloadConfigTBL_Config1_Bank0
export UnloadConfigTBL_Total_Bank1
export UnloadConfigTBL_Total_Bank0
AREA lit(rom, rel)
0000 LoadConfigTBL_Config1_Bank0:
0000 FF db ffh
0001 LoadConfigTBL_Config1_Bank1:
0001 FF db ffh
0002 UnloadConfigTBL_Config1_Bank0:
0002 FF db ffh
0003 UnloadConfigTBL_Config1_Bank1:
0003 FF db ffh
0004
0004 FF db ffh
0005 LoadConfigTBL_hbtouchkey_Ordered:
0005 ; Ordered Global Register values
0005 7110 or F, FLAG_XIO_MASK
0007 6200A8 mov reg[00h], a8h ; Port_0_DriveMode_0 register (PRT0DM0)
000A 620157 mov reg[01h], 57h ; Port_0_DriveMode_1 register (PRT0DM1)
000D 70EF and F, ~FLAG_XIO_MASK
000F 620357 mov reg[03h], 57h ; Port_0_DriveMode_2 register (PRT0DM2)
0012 620200 mov reg[02h], 00h ; Port_0_GlobalSelect register (PRT0GS)
0015 7110 or F, FLAG_XIO_MASK
0017 620200 mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
001A 620300 mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
001D 70EF and F, ~FLAG_XIO_MASK
001F 620100 mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
0022 7110 or F, FLAG_XIO_MASK
0024 62040B mov reg[04h], 0bh ; Port_1_DriveMode_0 register (PRT1DM0)
0027 6205F7 mov reg[05h], f7h ; Port_1_DriveMode_1 register (PRT1DM1)
002A 70EF and F, ~FLAG_XIO_MASK
002C 6207F7 mov reg[07h], f7h ; Port_1_DriveMode_2 register (PRT1DM2)
002F 620600 mov reg[06h], 00h ; Port_1_GlobalSelect register (PRT1GS)
0032 7110 or F, FLAG_XIO_MASK
0034 620600 mov reg[06h], 00h ; Port_1_IntCtrl_0 register (PRT1IC0)
0037 620700 mov reg[07h], 00h ; Port_1_IntCtrl_1 register (PRT1IC1)
003A 70EF and F, ~FLAG_XIO_MASK
003C 620500 mov reg[05h], 00h ; Port_1_IntEn register (PRT1IE)
003F 7110 or F, FLAG_XIO_MASK
0041 620800 mov reg[08h], 00h ; Port_2_DriveMode_0 register (PRT2DM0)
0044 6209FF mov reg[09h], ffh ; Port_2_DriveMode_1 register (PRT2DM1)
0047 70EF and F, ~FLAG_XIO_MASK
0049 620BFF mov reg[0bh], ffh ; Port_2_DriveMode_2 register (PRT2DM2)
004C 620A00 mov reg[0ah], 00h ; Port_2_GlobalSelect register (PRT2GS)
004F 7110 or F, FLAG_XIO_MASK
0051 620A00 mov reg[0ah], 00h ; Port_2_IntCtrl_0 register (PRT2IC0)
0054 620B00 mov reg[0bh], 00h ; Port_2_IntCtrl_1 register (PRT2IC1)
0057 70EF and F, ~FLAG_XIO_MASK
0059 620900 mov reg[09h], 00h ; Port_2_IntEn register (PRT2IE)
005C 7110 or F, FLAG_XIO_MASK
005E 620C02 mov reg[0ch], 02h ; Port_3_DriveMode_0 register (PRT3DM0)
0061 620D0F mov reg[0dh], 0fh ; Port_3_DriveMode_1 register (PRT3DM1)
0064 70EF and F, ~FLAG_XIO_MASK
0066 620F0F mov reg[0fh], 0fh ; Port_3_DriveMode_2 register (PRT3DM2)
0069 620E02 mov reg[0eh], 02h ; Port_3_GlobalSelect register (PRT3GS)
006C 7110 or F, FLAG_XIO_MASK
006E 620E00 mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
0071 620F00 mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
0074 70EF and F, ~FLAG_XIO_MASK
0076 620D00 mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
0079 7F ret
007A LoadConfigTBL_hbtouchkey_Bank0:
007A ; Global Register values
007A 6009 db 60h, 09h ; AnalogColumnInputSelect register (AMX_IN)
007C 6400 db 64h, 00h ; AnalogComparatorControl0 register (CMP_CR0)
007E 6600 db 66h, 00h ; AnalogComparatorControl1 register (CMP_CR1)
0080 6100 db 61h, 00h ; AnalogMuxBusConfig register (AMUXCFG)
0082 E600 db e6h, 00h ; DecimatorControl_0 register (DEC_CR0)
0084 E700 db e7h, 00h ; DecimatorControl_1 register (DEC_CR1)
0086 D644 db d6h, 44h ; I2CConfig register (I2CCFG)
0088 6200 db 62h, 00h ; PWM_Control register (PWM_CR)
008A B000 db b0h, 00h ; Row_0_InputMux register (RDI0RI)
008C B100 db b1h, 00h ; Row_0_InputSync register (RDI0SYN)
008E B200 db b2h, 00h ; Row_0_LogicInputAMux register (RDI0IS)
0090 B333 db b3h, 33h ; Row_0_LogicSelect_0 register (RDI0LT0)
0092 B433 db b4h, 33h ; Row_0_LogicSelect_1 register (RDI0LT1)
0094 B501 db b5h, 01h ; Row_0_OutputDrive_0 register (RDI0SRO0)
0096 B600 db b6h, 00h ; Row_0_OutputDrive_1 register (RDI0SRO1)
0098 ; Instance name CSD, User Module CSD
0098 ; Instance name CSD, Block Name CMP(ACE01)
0098 762F db 76h, 2fh ;CSD_ACE_CONTROL1_REG(ACE01CR1)
009A 7700 db 77h, 00h ;CSD_ACE_CONTROL2_REG(ACE01CR2)
009C ; Instance name CSD, Block Name CMP0(ACE00)
009C 7200 db 72h, 00h ;CSD_(ACE00CR1)
009E 7300 db 73h, 00h ;CSD_(ACE00CR2)
00A0 ; Instance name CSD, Block Name CMP_REF(ASE11)
00A0 6900 db 69h, 00h ;CSD_ADC_CONTROL_REG(ADC1_CR)
00A2 8400 db 84h, 00h ;CSD_ASE_CONTROL_REG(ASE11CR0)
00A4 ; Instance name CSD, Block Name CNT(DBB00)
00A4 2300 db 23h, 00h ;CSD_CNT_CONTROL_REG(DBB00CR0)
00A6 2100 db 21h, 00h ;CSD_CNT_PERIOD_REG(DBB00DR1)
00A8 2200 db 22h, 00h ;CSD_CNT_COMPARE_REG(DBB00DR2)
00AA ; Instance name CSD, Block Name PRS16_LSB(DBB01)
00AA 2700 db 27h, 00h ;CSD_PRS_CONTROL_LSB_REG(DBB01CR0)
00AC 2500 db 25h, 00h ;CSD_PRS_POLY_LSB_REG(DBB01DR1)
00AE 2600 db 26h, 00h ;CSD_PRS_SEED_LSB_REG(DBB01DR2)
00B0 ; Instance name CSD, Block Name PRS16_MSB(DCB02)
00B0 2B00 db 2bh, 00h ;CSD_PRS_CONTROL_MSB_REG(DCB02CR0)
00B2 2900 db 29h, 00h ;CSD_PRS_POLY_MSB_REG(DCB02DR1)
00B4 2A00 db 2ah, 00h ;CSD_PRS_SEED_MSB_REG(DCB02DR2)
00B6 ; Instance name I2CHW, User Module I2CHW
00B6 ; Instance name Timer8, User Module Timer8
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -