📄 psocconfigtbl.lst
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481
482 ;;=============================================================================
483 ;; M8C System Macros
484 ;; These macros should be used when their functions are needed.
485 ;;=============================================================================
486
487 ;----------------------------------------------------
488 ; Swapping Register Banks
489 ;----------------------------------------------------
490 macro M8C_SetBank0
491 and F, ~FLAG_XIO_MASK
492 1E64 endm
493
494 macro M8C_SetBank1
495 or F, FLAG_XIO_MASK
496 1E64 endm
497
498 ;----------------------------------------------------
499 ; Global Interrupt Enable/Disable
500 ;----------------------------------------------------
501 macro M8C_EnableGInt
502 or F, FLAG_GLOBAL_IE
503 1E64 endm
504
505 macro M8C_DisableGInt
506 and F, ~FLAG_GLOBAL_IE
507 1E64 endm
508
509 ;----------------------------------------------------
510 ; Enable/Disable Interrupt Mask
511 ;
512 ; Use the following macros to enable/disable
513 ; bits in the Interrupt mask registers,
514 ; INT_MSK0, INT_MSK1 or INT_MSK3.
515 ;
516 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
517 ; M8C_EnableIntMask INT_MSKN, MASK
518 ;
519 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
520 ; and MASK is the bit set to enable or disable
521 ;----------------------------------------------------
522 ; Disable Interrupt Bit Mask(s)
523 macro M8C_DisableIntMask
524 and reg[@0], ~@1 ; disable specified interrupt enable bit
525 1E64 endm
526
527 ; Enable Interrupt Bit Mask(s)
528 macro M8C_EnableIntMask
529 or reg[@0], @1 ; enable specified interrupt enable bit
530 1E64 endm
531
532 ;----------------------------------------------------
533 ; Clear Posted Interrupt Flag Mask
534 ;
535 ; Use the following macros to clear the
536 ; bits in the Interrupt Clear registers,
537 ; INT_CLR0, INT_CLR1 or INT_CLR3.
538 ; Usage: M8C_ClearIntFlag INT_CLRN, MASK
539 ;
540 ; where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
541 ; and MASK is the bit set to enable or disable
542 ;----------------------------------------------------
543 macro M8C_ClearIntFlag
544 mov reg[@0], ~@1 ; clear specified interrupt enable bit
545 1E64 endm
546
547 ;----------------------------------------------------
548 ; Power-On Reset & WatchDog Timer Functions
549 ;----------------------------------------------------
550 macro M8C_EnableWatchDog
551 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
552 1E64 endm
553
554 macro M8C_ClearWDT
555 mov reg[RES_WDT], 00h
556 1E64 endm
557
558 macro M8C_ClearWDTAndSleep
559 mov reg[RES_WDT], 38h
560 1E64 endm
561
562 ;----------------------------------------------------
563 ; Sleep, CPU Stop & Software Reset
564 ;----------------------------------------------------
565 macro M8C_Sleep
566 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
567 ; The next instruction to be executed depends on the state of the
568 ; various interrupt enable bits. If some interrupts are enabled
569 ; and the global interrupts are disabled, the next instruction will
570 ; be the one that follows the invocation of this macro. If global
571 ; interrupts are also enabled then the next instruction will be
572 ; from the interrupt vector table. If no interrupts are enabled
573 ; then the CPU sleeps forever.
574 1E64 endm
575
576 macro M8C_Stop
577 ; In general, you probably don't want to do this, but here's how:
578 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
579 ; Next instruction to be executed is located in the interrupt
580 ; vector table entry for Power-On Reset.
581 1E64 endm
582
583 macro M8C_Reset
584 ; Restore CPU to the power-on reset state.
585 mov A, 0
586 SSC
587 ; Next non-supervisor instruction will be at interrupt vector 0.
588 1E64 endm
589
590 ;----------------------------------------------------
591 ; ImageCraft Code Compressor Actions
592 ;----------------------------------------------------
593 ; Suspend Code Compressor
594 ; Must not span a RET or RETI instruction
595 ; without resuming code compression
596 macro Suspend_CodeCompressor
597 or F, 0
598 1E64 endm
599
600 ; Resume Code Compression
601 macro Resume_CodeCompressor
602 add SP, 0
603 1E64 endm
1 ; Generated by PSoC Designer ???
2 ;
3 include "m8c.inc"
4 ; Personalization tables
5 export LoadConfigTBL_hbtouchkey_Bank1
6 export LoadConfigTBL_hbtouchkey_Bank0
7 export LoadConfigTBL_hbtouchkey_Ordered
8 export UnloadConfigTBL_hbtouchkey_Bank1
9 export UnloadConfigTBL_hbtouchkey_Bank0
10 export ReloadConfigTBL_hbtouchkey_Bank1
11 export ReloadConfigTBL_hbtouchkey_Bank0
12 export LoadConfigTBL_Config1_Bank1
13 export LoadConfigTBL_Config1_Bank0
14 export UnloadConfigTBL_Config1_Bank1
15 export UnloadConfigTBL_Config1_Bank0
16 export UnloadConfigTBL_Total_Bank1
17 export UnloadConfigTBL_Total_Bank0
18 AREA lit(rom, rel)
19 130C LoadConfigTBL_Config1_Bank0:
20 130C FF db ffh
21 130D LoadConfigTBL_Config1_Bank1:
22 130D FF db ffh
23 130E UnloadConfigTBL_Config1_Bank0:
24 130E FF db ffh
25 130F UnloadConfigTBL_Config1_Bank1:
26 130F FF db ffh
27
28 1310 FF db ffh
29 1311 LoadConfigTBL_hbtouchkey_Ordered:
32 1313 62 00 A8 mov reg[00h], a8h ; Port_0_DriveMode_0 register (PRT0DM0)
33 1316 62 01 57 mov reg[01h], 57h ; Port_0_DriveMode_1 register (PRT0DM1)
35 131B 62 03 57 mov reg[03h], 57h ; Port_0_DriveMode_2 register (PRT0DM2)
36 131E 62 02 00 mov reg[02h], 00h ; Port_0_GlobalSelect register (PRT0GS)
38 1323 62 02 00 mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
39 1326 62 03 00 mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
41 132B 62 01 00 mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
43 1330 62 04 0B mov reg[04h], 0bh ; Port_1_DriveMode_0 register (PRT1DM0)
44 1333 62 05 F7 mov reg[05h], f7h ; Port_1_DriveMode_1 register (PRT1DM1)
46 1338 62 07 F7 mov reg[07h], f7h ; Port_1_DriveMode_2 register (PRT1DM2)
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