📄 at_hw.h
字号:
#define BIST0_SRAM_FAIL 0x2 // 1: The SRAM failure is un-repairable because it has address
// decoder failure or more than 1 cell stuck-to-x failure.
#define BIST0_FUSE_FLAG 0x4 // 1: Indicating one cell has been fixed
// BIST Control and Status Register1(for the retry buffer of PCI Express)
#define REG_BIST1_CTRL 0x1420
#define BIST1_NOW 0x1 // 1: To trigger BIST0 logic. This bit stays high during the
// BIST process and reset to zero when BIST is done
#define BIST1_SRAM_FAIL 0x2 // 1: The SRAM failure is un-repairable because it has address
// decoder failure or more than 1 cell stuck-to-x failure.
#define BIST1_FUSE_FLAG 0x4
// SerDes Lock Detect Control and Status Register
#define REG_SERDES_LOCK 0x1424
#define SERDES_LOCK_DETECT 1 // 1: SerDes lock detected . This signal comes from Analog SerDes.
#define SERDES_LOCK_DETECT_EN 2 // 1: Enable SerDes Lock detect function.
// MAC Control Register
#define REG_MAC_CTRL 0x1480
#define MAC_CTRL_TX_EN 1 // 1: Transmit Enable
#define MAC_CTRL_RX_EN 2 // 1: Receive Enable
#define MAC_CTRL_TX_FLOW 4 // 1: Transmit Flow Control Enable
#define MAC_CTRL_RX_FLOW 8 // 1: Receive Flow Control Enable
#define MAC_CTRL_LOOPBACK 0x10 // 1: Loop back at G/MII Interface
#define MAC_CTRL_DUPLX 0x20 // 1: Full-duplex mode 0: Half-duplex mode
#define MAC_CTRL_ADD_CRC 0x40 // 1: Instruct MAC to attach CRC on all egress Ethernet frames
#define MAC_CTRL_PAD 0x80 // 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN
#define MAC_CTRL_LENCHK 0x100 // 1: Instruct MAC to check if length field matches the real packet length.
#define MAC_CTRL_HUGE_EN 0x200 // 1: receive Jumbo frame enable
#define MAC_CTRL_PRMLEN_SHIFT 10 // Preamble length, it?ˉs 0x07 by standard
#define MAC_CTRL_PRMLEN_MASK 0xf
#define MAC_CTRL_RMV_VLAN 0x4000 // 1: to remove VLAN Tag automatically from all receive packets
#define MAC_CTRL_PROMIS_EN 0x8000 // 1: Promiscuous Mode Enable
#define MAC_CTRL_TX_PAUSE 0x10000 // 1: transmit test pause
#define MAC_CTRL_SCNT 0x20000 // 1: shortcut slot time counter
#define MAC_CTRL_SRST_TX 0x40000 // 1: synchronized reset Transmit MAC module
#define MAC_CTRL_TX_SIMURST 0x80000 // 1: transmit simulation reset
#define MAC_CTRL_SPEED_SHIFT 20 // 2?ˉb10: gigabit 2?ˉb01:10M/100M
#define MAC_CTRL_SPEED_MASK 0x300000
#define MAC_CTRL_SPEED_1000 2
#define MAC_CTRL_SPEED_10_100 1
#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 // 1: transmit maximum backoff (half-duplex test bit)
#define MAC_CTRL_TX_HUGE 0x800000 // 1: transmit huge enable
#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 // 1: RX checksum enable
#define MAC_CTRL_MC_ALL_EN 0x2000000 // 1: upload all multicast frame without error to system
#define MAC_CTRL_BC_EN 0x4000000 // 1: upload all broadcast frame without error to system
#define MAC_CTRL_DBG 0x8000000 // 1: upload all received frame to system (Debug Mode)
// MAC IPG/IFG Control Register
#define REG_MAC_IPG_IFG 0x1484
#define MAC_IPG_IFG_IPGT_SHIFT 0 // Desired back to back inter-packet gap. The default is 96-bit time.
#define MAC_IPG_IFG_IPGT_MASK 0x7f
#define MAC_IPG_IFG_MIFG_SHIFT 8 // Minimum number of IFG to enforce in between RX frames.
#define MAC_IPG_IFG_MIFG_MASK 0xff // Frame gap below such IFP is dropped.
#define MAC_IPG_IFG_IPGR1_SHIFT 16 // 64bit Carrier-Sense window
#define MAC_IPG_IFG_IPGR1_MASK 0x7f //
#define MAC_IPG_IFG_IPGR2_SHIFT 24 // 96-bit IPG window
#define MAC_IPG_IFG_IPGR2_MASK 0x7f
// MAC STATION ADDRESS
#define REG_MAC_STA_ADDR 0x1488
// Hash table for multicast address
#define REG_RX_HASH_TABLE 0x1490
// MAC Half-Duplex Control Register
#define REG_MAC_HALF_DUPLX_CTRL 0x1498
#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 // Collision Window.
#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 // Retransmission maximum, afterwards the packet will be discarded.
#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 // 1: Allow the transmission of a packet which has been excessively deferred
#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 // 1: No back-off on collision, immediately start the retransmission.
#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 // 1: No back-off on backpressure, immediately start the transmission after back pressure
#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 // 1: Alternative Binary Exponential Back-off Enabled
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 // Maximum binary exponential number.
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 // IPG to start JAM for collision based flow control in half-duplex
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf // mode. In unit of 8-bit time.
// Maximum Frame Length Control Register
#define REG_MTU 0x149c
// Wake-On-Lan control register
#define REG_WOL_CTRL 0x14a0
#define WOL_PATTERN_EN 0x00000001
#define WOL_PATTERN_PME_EN 0x00000002
#define WOL_MAGIC_EN 0x00000004
#define WOL_MAGIC_PME_EN 0x00000008
#define WOL_LINK_CHG_EN 0x00000010
#define WOL_LINK_CHG_PME_EN 0x00000020
#define WOL_PATTERN_ST 0x00000100
#define WOL_MAGIC_ST 0x00000200
#define WOL_LINKCHG_ST 0x00000400
#define WOL_CLK_SWITCH_EN 0x00008000
#define WOL_PT0_EN 0x00010000
#define WOL_PT1_EN 0x00020000
#define WOL_PT2_EN 0x00040000
#define WOL_PT3_EN 0x00080000
#define WOL_PT4_EN 0x00100000
#define WOL_PT5_EN 0x00200000
#define WOL_PT6_EN 0x00400000
// WOL Length ( 2 DWORD )
#define REG_WOL_PATTERN_LEN 0x14a4
#define WOL_PT_LEN_MASK 0x7f
#define WOL_PT0_LEN_SHIFT 0
#define WOL_PT1_LEN_SHIFT 8
#define WOL_PT2_LEN_SHIFT 16
#define WOL_PT3_LEN_SHIFT 24
#define WOL_PT4_LEN_SHIFT 0
#define WOL_PT5_LEN_SHIFT 8
#define WOL_PT6_LEN_SHIFT 16
// Internal SRAM Partition Register
#define REG_SRAM_TRD_ADDR 0x1518
#define REG_SRAM_TRD_LEN 0x151C
#define REG_SRAM_RXF_ADDR 0x1520
#define REG_SRAM_RXF_LEN 0x1524
#define REG_SRAM_TXF_ADDR 0x1528
#define REG_SRAM_TXF_LEN 0x152C
#define REG_SRAM_TCPH_ADDR 0x1530
#define REG_SRAM_PKTH_ADDR 0x1532
// Load Ptr Register
#define REG_LOAD_PTR 0x1534 // Software sets this bit after the initialization of the head and tail
// addresses of all descriptors, as well as the following descriptor
// control register, which triggers each function block to load the head
// pointer to prepare for the operation. This bit is then self-cleared
// after one cycle.
// Descriptor Control register
#define REG_RXF3_BASE_ADDR_HI 0x153C
// Descriptor Control register
#define REG_DESC_BASE_ADDR_HI 0x1540
#define REG_HOST_RXF0_PAGE0_LO 0x1544
#define REG_HOST_RXF0_PAGE1_LO 0x1548
#define REG_TPD_BASE_ADDR_LO 0x154C
#define REG_RXF1_BASE_ADDR_HI 0x1550
#define REG_RXF2_BASE_ADDR_HI 0x1554
#define REG_HOST_RXFPAGE_SIZE 0x1558
#define REG_TPD_RING_SIZE 0x155C
// RSS about
#define REG_RSS_KEY0 0x14B0
#define REG_RSS_KEY1 0x14B4
#define REG_RSS_KEY2 0x14B8
#define REG_RSS_KEY3 0x14BC
#define REG_RSS_KEY4 0x14C0
#define REG_RSS_KEY5 0x14C4
#define REG_RSS_KEY6 0x14C8
#define REG_RSS_KEY7 0x14CC
#define REG_RSS_KEY8 0x14D0
#define REG_RSS_KEY9 0x14D4
#define REG_IDT_TABLE4 0x14E0
#define REG_IDT_TABLE5 0x14E4
#define REG_IDT_TABLE6 0x14E8
#define REG_IDT_TABLE7 0x14EC
#define REG_IDT_TABLE0 0x1560
#define REG_IDT_TABLE1 0x1564
#define REG_IDT_TABLE2 0x1568
#define REG_IDT_TABLE3 0x156C
#define REG_IDT_TABLE REG_IDT_TABLE0
#define REG_RSS_HASH_VALUE 0x1570
#define REG_RSS_HASH_FLAG 0x1574
#define REG_BASE_CPU_NUMBER 0x157C
// TXQ Control Register
#define REG_TXQ_CTRL 0x1580
#define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF
#define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0
#define TXQ_CTRL_EN 0x20 // 1: Enable TXQ
#define TXQ_CTRL_ENH_MODE 0x40 // Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched.
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 // Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length.
#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
// Jumbo packet Threshold for task offload
#define REG_TX_EARLY_TH 0x1584 // Jumbo frame threshold in QWORD unit. Packet greater than
// JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded.
#define TX_TX_EARLY_TH_MASK 0x7ff
#define TX_TX_EARLY_TH_SHIFT 0
// RXQ Control Register
#define REG_RXQ_CTRL 0x15A0
#define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
#define RXQ_CTRL_PBA_ALIGN_64 1
#define RXQ_CTRL_PBA_ALIGN_128 2
#define RXQ_CTRL_PBA_ALIGN_256 3
#define RXQ_CTRL_Q1_EN 0x10
#define RXQ_CTRL_Q2_EN 0x20
#define RXQ_CTRL_Q3_EN 0x40
#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80
#define RXQ_CTRL_HASH_TLEN_SHIFT 8
#define RXQ_CTRL_HASH_TLEN_MASK 0xFF
#define RXQ_CTRL_HASH_TYPE_IPV4 0x10000
#define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000
#define RXQ_CTRL_HASH_TYPE_IPV6 0x40000
#define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000
#define RXQ_CTRL_RSS_MODE_DISABLE 0
#define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000
#define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000
#define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000
#define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000
#define RXQ_CTRL_HASH_ENABLE 0x20000000
#define RXQ_CTRL_CUT_THRU_EN 0x40000000
#define RXQ_CTRL_EN 0x80000000
// Rx jumbo packet threshold and rrd retirement timer
#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
#define RXQ_JMBOSZ_TH_MASK 0x7ff // Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit. When the packet
// length greater than or equal to this value, RXQ shall start cut-through forwarding of the received packet.
#define RXQ_JMBOSZ_TH_SHIFT 0 // RRD retirement timer. Decrement by 1 after every 512ns passes.
#define RXQ_JMBO_LKAH_MASK 0xf
#define RXQ_JMBO_LKAH_SHIFT 11
// RXF flow control register
#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
// DMA Engine Control Register
#define REG_DMA_CTRL 0x15C0
#define DMA_CTRL_DMAR_IN_ORDER 0x1
#define DMA_CTRL_DMAR_ENH_ORDER 0x2
#define DMA_CTRL_DMAR_OUT_ORDER 0x4
#define DMA_CTRL_RCB_VALUE 0x8
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
#define DMA_CTRL_DMAR_REQ_PRI 0x400
#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F
#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
#define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF
#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
#define DMA_CTRL_TXCMB_EN 0x100000
#define DMA_CTRL_RXCMB_EN 0x200000
// CMB/SMB Control Register
#define REG_SMB_STAT_TIMER 0x15C4
#define REG_TRIG_RRD_THRESH 0x15CA // w
#define REG_TRIG_TPD_THRESH 0x15C8 // w
#define REG_TRIG_TXTIMER 0x15CC // w
#define REG_TRIG_RXTIMER 0x15CE // w
// HOST RXF Page 1,2,3 address
#define REG_HOST_RXF1_PAGE0_LO 0x15D0
#define REG_HOST_RXF1_PAGE1_LO 0x15D4
#define REG_HOST_RXF2_PAGE0_LO 0x15D8
#define REG_HOST_RXF2_PAGE1_LO 0x15DC
#define REG_HOST_RXF3_PAGE0_LO 0x15E0
#define REG_HOST_RXF3_PAGE1_LO 0x15E4
// Mail box
#define REG_MB_RXF1_RADDR 0x15B4
#define REG_MB_RXF2_RADDR 0x15B8
#define REG_MB_RXF3_RADDR 0x15BC
#define REG_MB_TPD_PROD_IDX 0x15F0
// RXF-Page 0-3 PageNo & Valid bit
#define REG_HOST_RXF0_PAGE0_VLD 0x15F4
#define HOST_RXF_VALID 1
#define HOST_RXF_PAGENO_SHIFT 1
#define HOST_RXF_PAGENO_MASK 0x7F
#define REG_HOST_RXF0_PAGE1_VLD 0x15F5
#define REG_HOST_RXF1_PAGE0_VLD 0x15F6
#define REG_HOST_RXF1_PAGE1_VLD 0x15F7
#define REG_HOST_RXF2_PAGE0_VLD 0x15F8
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -