📄 at_hw.h
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/*
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* There are a lot of defines in here that are unused and/or have cryptic
* names. Please leave them alone, as they're the closest thing we have
* to a spec from Atheros at present. *ahem* -- CHS
*/
#ifndef _ATHEROS_HW_H__
#define _ATHEROS_HW_H__
#include "at_osdep.h"
#define _AT_ATTRIB_PACK_ __attribute__ ((packed))
struct at_adapter;
struct at_hw;
/* function prototype */
s32 at_reset_hw(struct at_hw* hw);
s32 at_read_mac_addr(struct at_hw* hw);
s32 at_init_hw(struct at_hw* hw);
s32 at_phy_setup_autoneg_adv(struct at_hw *hw);
s32 at_phy_commit(struct at_hw *hw);
s32 at_get_speed_and_duplex(struct at_hw *hw, u16 *speed, u16 *duplex);
u32 at_auto_get_fc(struct at_adapter* adapter, u16 duplex);
u32 at_hash_mc_addr(struct at_hw *hw, u8 *mc_addr);
void at_hash_set(struct at_hw *hw, u32 hash_value);
s32 at_read_phy_reg(struct at_hw *hw, u16 reg_addr, u16 *phy_data);
s32 at_write_phy_reg(struct at_hw *hw, u32 reg_addr, u16 phy_data);
void at_read_pci_cfg(struct at_hw* hw, u32 reg, u16 *value);
void at_write_pci_cfg(struct at_hw* hw, u32 reg, u16 *value);
s32 at_validate_mdi_setting(struct at_hw* hw);
void set_mac_addr(struct at_hw* hw);
int get_permanent_address(struct at_hw* hw);
boolean_t read_eeprom(struct at_hw* hw, u32 Offset, u32* pValue);
boolean_t write_eeprom(struct at_hw* hw, u32 offset, u32 value);
s32 at_phy_enter_power_saving(struct at_hw* hw);
s32 at_phy_leave_power_saving(struct at_hw* hw);
s32 at_phy_init(struct at_hw* hw);
int check_eeprom_exist(struct at_hw* hw);
void at_force_ps(struct at_hw* hw);
s32 at_restart_autoneg(struct at_hw *hw);
/* register definition */
/* register definition */
#define REG_PM_CTRLSTAT 0x44
#define REG_PCIE_CAP_LIST 0x58
#define REG_DEVICE_CAP 0x5C
#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
#define REG_DEVICE_CTRL 0x60
#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
#define REG_VPD_CAP 0x6C
#define VPD_CAP_ID_MASK 0xff
#define VPD_CAP_ID_SHIFT 0
#define VPD_CAP_NEXT_PTR_MASK 0xFF
#define VPD_CAP_NEXT_PTR_SHIFT 8
#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
#define VPD_CAP_VPD_ADDR_SHIFT 16
#define VPD_CAP_VPD_FLAG 0x80000000
#define REG_VPD_DATA 0x70
#define REG_SPI_FLASH_CTRL 0x200
#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
#define SPI_FLASH_CTRL_STS_WEN 0x2
#define SPI_FLASH_CTRL_STS_WPEN 0x80
#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
#define SPI_FLASH_CTRL_INS_MASK 0x7
#define SPI_FLASH_CTRL_INS_SHIFT 8
#define SPI_FLASH_CTRL_START 0x800
#define SPI_FLASH_CTRL_EN_VPD 0x2000
#define SPI_FLASH_CTRL_LDSTART 0x8000
#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
#define REG_SPI_ADDR 0x204
#define REG_SPI_DATA 0x208
#define REG_SPI_FLASH_CONFIG 0x20C
#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
#define REG_SPI_FLASH_OP_PROGRAM 0x210
#define REG_SPI_FLASH_OP_SC_ERASE 0x211
#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
#define REG_SPI_FLASH_OP_RDID 0x213
#define REG_SPI_FLASH_OP_WREN 0x214
#define REG_SPI_FLASH_OP_RDSR 0x215
#define REG_SPI_FLASH_OP_WRSR 0x216
#define REG_SPI_FLASH_OP_READ 0x217
#define REG_TWSI_CTRL 0x218
#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
#define TWSI_CTRL_LD_OFFSET_SHIFT 0
#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
#define TWSI_CTRL_SW_LDSTART 0x800
#define TWSI_CTRL_HW_LDSTART 0x1000
#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F
#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
#define TWSI_CTRL_LD_EXIST 0x400000
#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
#define TWSI_CTRL_FREQ_SEL_100K 0
#define TWSI_CTRL_FREQ_SEL_200K 1
#define TWSI_CTRL_FREQ_SEL_300K 2
#define TWSI_CTRL_FREQ_SEL_400K 3
#define TWSI_CTRL_SMB_SLV_ADDR
#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
#define REG_PCIE_DEV_MISC_CTRL 0x21C
#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
#define REG_PCIE_PHYMISC 0x1000
#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
#define REG_LTSSM_TEST_MODE 0x12FC
#define LTSSM_TEST_MODE_DEF 0xE000
// Selene Master Control Register
#define REG_MASTER_CTRL 0x1400
#define MASTER_CTRL_SOFT_RST 0x1
#define MASTER_CTRL_MTIMER_EN 0x2
#define MASTER_CTRL_ITIMER_EN 0x4
#define MASTER_CTRL_MANUAL_INT 0x8
#define MASTER_CTRL_ITIMER2_EN 0x20
#define MASTER_CTRL_INT_RDCLR 0x40
#define MASTER_CTRL_LED_MODE 0x200
#define MASTER_CTRL_REV_NUM_SHIFT 16
#define MASTER_CTRL_REV_NUM_MASK 0xff
#define MASTER_CTRL_DEV_ID_SHIFT 24
#define MASTER_CTRL_DEV_ID_MASK 0xff
// Timer Initial Value Register
#define REG_MANUAL_TIMER_INIT 0x1404
// IRQ ModeratorTimer Initial Value Register
#define REG_IRQ_MODU_TIMER_INIT 0x1408 // w
#define REG_IRQ_MODU_TIMER2_INIT 0x140A // w
#define REG_GPHY_CTRL 0x140C
#define GPHY_CTRL_EXT_RESET 1
#define GPHY_CTRL_PIPE_MOD 2
#define GPHY_CTRL_TEST_MODE_MASK 3
#define GPHY_CTRL_TEST_MODE_SHIFT 2
#define GPHY_CTRL_BERT_START 0x10
#define GPHY_CTRL_GATE_25M_EN 0x20
#define GPHY_CTRL_LPW_EXIT 0x40
#define GPHY_CTRL_PHY_IDDQ 0x80
#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
#define GPHY_CTRL_PCLK_SEL_DIS 0x200
#define GPHY_CTRL_HIB_EN 0x400
#define GPHY_CTRL_HIB_PULSE 0x800
#define GPHY_CTRL_SEL_ANA_RST 0x1000
#define GPHY_CTRL_PHY_PLL_ON 0x2000
#define GPHY_CTRL_PWDOWN_HW 0x4000
#define GPHY_CTRL_DEFAULT (\
GPHY_CTRL_SEL_ANA_RST |\
GPHY_CTRL_HIB_PULSE |\
GPHY_CTRL_HIB_EN )
#define GPHY_CTRL_PW_WOL_DIS (\
GPHY_CTRL_SEL_ANA_RST |\
GPHY_CTRL_HIB_PULSE |\
GPHY_CTRL_HIB_EN |\
GPHY_CTRL_PWDOWN_HW |\
GPHY_CTRL_PCLK_SEL_DIS |\
GPHY_CTRL_PHY_IDDQ )
// IRQ Anti-Lost Timer Initial Value Register
//#define REG_IRQ_CLR_TIMER 0x140c // Maximum allowance for software to clear the interrupt.
// IRQ Anti-Lost Timer Initial Value Register
#define REG_CMBDISDMA_TIMER 0x140E
// Block IDLE Status Register
#define REG_IDLE_STATUS 0x1410
#define IDLE_STATUS_RXMAC 1 // 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling
#define IDLE_STATUS_TXMAC 2 // 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling
#define IDLE_STATUS_RXQ 4 // 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling
#define IDLE_STATUS_TXQ 8 // 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling
#define IDLE_STATUS_DMAR 0x10 // 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling
#define IDLE_STATUS_DMAW 0x20 // 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling
#define IDLE_STATUS_SMB 0x40 // 1: SMB state machine is in non-IDLE state. 0: SMB is idling
#define IDLE_STATUS_CMB 0x80 // 1: CMB state machine is in non-IDLE state. 0: CMB is idling
// MDIO Control Register
#define REG_MDIO_CTRL 0x1414
#define MDIO_DATA_MASK 0xffff // On MDIO write, the 16-bit control data to write to PHY MII management register;
#define MDIO_DATA_SHIFT 0 // On MDIO read, the 16-bit status data that was read from the PHY MII management register.
#define MDIO_REG_ADDR_MASK 0x1f // MDIO register address
#define MDIO_REG_ADDR_SHIFT 16
#define MDIO_RW 0x200000 // 1: read, 0: write
#define MDIO_SUP_PREAMBLE 0x400000 // Suppress preamble
#define MDIO_START 0x800000 // Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle.
#define MDIO_CLK_SEL_SHIFT 24
#define MDIO_CLK_25_4 0
#define MDIO_CLK_25_6 2
#define MDIO_CLK_25_8 3
#define MDIO_CLK_25_10 4
#define MDIO_CLK_25_14 5
#define MDIO_CLK_25_20 6
#define MDIO_CLK_25_28 7
#define MDIO_BUSY 0x8000000
#define MDIO_AP_EN 0x10000000
#define MDIO_WAIT_TIMES 10
// MII PHY Status Register
#define REG_PHY_STATUS 0x1418
#define PHY_STATUS_100M 0x20000
#define PHY_STATUS_EMI_CA 0x40000
// BIST Control and Status Register0 (for the Packet Memory)
#define REG_BIST0_CTRL 0x141c
#define BIST0_NOW 0x1 // 1: To trigger BIST0 logic. This bit stays high during the
// BIST process and reset to zero when BIST is done
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