vsc8601_phy.c

TP-LINK公司TL-WR941N无线路由器的Bootloader U_BOOT源代码

/* vsc8601.h
 *
 * History:
 * Jan 14, 2007 wclewis ready common BDI/ECOS/Linux
 *
 *
 * 1) Routine uses MII interface to query the specified device.
 *
 * 2) If the device is a VSC8201 or VSC8601 routine initializes
 *    device using Vitesse specific routines.
 *
 * 3) If device is a IEEE complient device the device is 
 *    initialized in a generic fashion.
 *
 * 4) During query the PHY address is captured and used to 
 *    initialize the phy table. This has been tested for
 *    the VSC8201, VSC8601 and ICPLUS.
 */

#ifdef __BDI
#include "bdi.h"
#else
#ifdef __ECOS
#if defined(CYGNUM_USE_ENET_VERBOSE)
#   undef  VERBOSE
#   define VERBOSE CYGNUM_USE_ENET_VERBOSE
#else
#   define VERBOSE 0
#endif 
#define generic_printk             DEBUG_PRINTF
#define generic_udelay             A_UDELAY
#else
#include <config.h>
#include <linux/types.h>
#include <common.h>
#include <miiphy.h>
#include "phy.h"
#include "vsc8601_phy.h"
#define generic_printk             printf
#define generic_udelay             udelay
#endif
#endif

#ifndef VERBOSE
#define  VERBOSE           1
#endif

#include "vsc8601_phy.h"

typedef struct {
  uint16_t     is_enet_port;
  uint16_t     mac_unit;
  uint16_t     phy_addr;
  uint32_t     id;
  uint16_t     status;
}vsc8601_phy_t;

static uint16_t nmbr_phys = 0;
static vsc8601_phy_t phy_info[] = {
  {
    is_enet_port: 0,
    mac_unit    : 0,
    phy_addr    : 0
  },
  {
    is_enet_port: 0,
    mac_unit    : 0,
    phy_addr    : 0
  },
  {
    is_enet_port: 0,
    mac_unit    : 0,
    phy_addr    : 0
  },
  {
    is_enet_port: 0,
    mac_unit    : 0,
    phy_addr    : 0
  },
  {
    is_enet_port: 0,
    mac_unit    : 0,
    phy_addr    : 0
  },
  {
    is_enet_port: 0,
    mac_unit    : 0,
    phy_addr    : 0
  }
};

static uint16_t
ag7100_mii_read(uint32_t phybase, uint16_t phyaddr, uint16_t reg)
{
    uint16_t val;

    phy_reg_read(phybase, phyaddr, reg, &val);
    return val;
}

static void
ag7100_mii_write(uint32_t phybase, uint16_t phyaddr, uint16_t reg, uint32_t val)
{
    phy_reg_write(phybase, phyaddr, reg, val);
}

#if 0
static vsc8601_phy_t *
vsc8601_phy_find(int unit)
{
  int i;
  vsc8601_phy_t *phy;
  
  for(i = 0; i < sizeof(phy_info)/sizeof(phy_info[0]); i++) {
    phy = &phy_info[i];
    if (phy->is_enet_port && (phy->mac_unit == unit))
      return phy;
  }
  generic_printk(" ERROR: Did not find unit %d\n", unit);
  return NULL;
}
#endif

/* Base read/write routines built on ag7100_mii_ macros */

static inline void
vsc8601_phy_mii_write_main(int unit, uint32_t phy_addr, uint8_t reg, uint16_t data)
{
  ag7100_mii_write(unit, phy_addr, 31,  0);
  ag7100_mii_write(unit, phy_addr, reg, data);
}

static inline void 
vsc8601_phy_mii_write_ex(int unit, uint32_t phy_addr, uint8_t reg, uint16_t data)
{
  ag7100_mii_write(unit, phy_addr, 31,  1);
  ag7100_mii_write(unit, phy_addr, reg, data);
}

static inline uint16_t  
vsc8601_phy_mii_read_main(int unit, uint32_t phy_addr, uint8_t reg)
{
  ag7100_mii_write(unit, phy_addr, 31,  0);
  return ag7100_mii_read(unit, phy_addr, reg);
}

static inline uint16_t 
vsc8601_phy_mii_read_ex(int unit, uint32_t phy_addr, uint8_t reg)
{
  uint16_t val;
  ag7100_mii_write(unit, phy_addr, 31,  1);
  val = ag7100_mii_read(unit, phy_addr, reg);
  ag7100_mii_write(unit, phy_addr, 31,  0);
  return val;
}

/* Super simple routine to make it easier to print bits */

static void
vsc8601_phy_print_val_bit_desc (uint16_t val, char *fieldName, char *bit_descriptions[]) 
{
  int ii;
  char *p2;
  
  generic_printk(" %s=%04x ", fieldName, val);
  for (ii=0;ii<16; ii++) {
    p2 = val & 1<<(15-ii) ? bit_descriptions[ii*2] : bit_descriptions[ii*2+1];
    if (p2 && p2[0])      
        generic_printk("    %s\n", p2);
  }
}

/* **************************************************************************** 
 *
 * For each register of interest:
 * 1) register read
 * 2) register print if there are alot of fields or bits
 * 3) register write if there may be a need to write
 * 4) masked write if there is a write and there are bits.
 *
 * **************************************************************************** */

/* mode control */

CEXTERN uint16_t 
vsc8601_phy_mii_read_mode_ctrl(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 0);
}

static char *mode_ctrl_desc[16*2] = {
  "sreset","", /* 15 */
  "loopback", "", /* 14 */
  "f100","", /* 13 */
  "auto-eg","", /* 12 */
  "pwr-dwn","", /* 11 */
  "isolate","", /* 10 */
  "restar-auto-neg","", /*  9 */
  "full-duplex","half-duplex", /*  8 */
  "ctest","", /*  7 */
  "f1000","", /*  6 */
  "","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "","", /*  2 */
  "","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_mode_ctrl(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "mode_ctr        (00 )", mode_ctrl_desc);
}

CEXTERN void 
vsc8601_phy_mii_write_mode_ctrl(int unit, uint32_t phy_addr, uint16_t reg )
{
  vsc8601_phy_mii_write_main(unit, phy_addr, 0, reg);
}

CEXTERN void 
vsc8601_phy_mii_rmw_ctrl(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_mii_read_mode_ctrl(unit, phy_addr); 
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_mii_write_mode_ctrl(unit, phy_addr, reg);
}

/* mode status */

CEXTERN uint16_t  
vsc8601_phy_mii_read_mode_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 1);
}

static char *mode_status_desc[16*2] = {
  "","", /* 15 */
  "","", /* 14 */
  "","", /* 13 */
  "","", /* 12 */
  "","", /* 11 */
  "","", /* 10 */
  "","", /*  9 */
  "","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "auto-neg-cmplt","", /*  5 */
  "rem-fault","", /*  4 */
  "auto-neg-cap","", /*  3 */
  "link-up","", /*  2 */
  "jabber","", /*  1 */
  "ex-cap","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_mode_status(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "mode_status     (01 )", mode_status_desc);
}

/* phy identification */

CEXTERN uint16_t 
vsc8601_phy_mii_read_id1(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 2);
}

CEXTERN uint16_t 
vsc8601_phy_mii_read_id2(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 3);
}

/* gige control R/W */

CEXTERN uint16_t 
vsc8601_phy_mii_read_gige_ctrl(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 9);
}

static char *gige_ctrl_desc[16*2] = {
  "distortion-test","", /* 15 */
  "jitter-test","", /* 14 */
  "waveform-test","", /* 13 */
  "man-cfg","", /* 12 */
  "master","", /* 11 */
  "","", /* 10 */
  "","", /*  9 */
  "","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "","", /*  2 */
  "","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_gige_ctrl(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "gige_ctrl       (09 )", gige_ctrl_desc);
}

CEXTERN void  
vsc8601_phy_mii_write_gige_ctrl(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_main(unit, phy_addr, 9, reg);
}

CEXTERN void 
vsc8601_phy_rmw_gige_ctrl(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_mii_read_gige_ctrl(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_mii_write_gige_ctrl(unit, phy_addr, reg);
}

/* gige status RO */

CEXTERN uint16_t  
vsc8601_phy_read_gige_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 10);
}

static char *gige_status_desc[16*2] = {
  "ms-fault","", /* 15 */
  "is-master","", /* 14 */
  "loc-rcv-ok","", /* 13 */
  "rem-rcv-ok","", /* 12 */
  "fdx-cap","", /* 11 */
  "hdx-cap","", /* 10 */
  "","", /*  9 */
  "","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "","", /*  2 */
  "","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_gige_status(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, " gige_status     (10 )", gige_status_desc);
  generic_printk("    idle-err-cnt: %02x\n", val&0xff);
}

/* gige status extension 1 todo */

/* 100 base_t status extension RO */

CEXTERN uint16_t  
vsc8601_phy_read_100_status_ex(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 16);
}

static char *l00_status_ex_desc[16*2] = {
  "descram-lock","", /* 15 */
  "descram-err","", /* 14 */
  "disc","", /* 13 */
  "link-act","", /* 12 */
  "rcv-err","", /* 11 */
  "xmt-err","", /* 10 */
  "sos-err","", /*  9 */
  "","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "","", /*  2 */
  "","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_100_status_ex(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "100_status_ex   (16 )", l00_status_ex_desc);
}

/* gige status extention 2 RO */

CEXTERN uint16_t 
vsc8601_phy_read_gige_status_ex_2(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 17);
}

static char *gige_status_ex_2_desc[16*2] = {
  "descram-lock","", /* 15 */
  "descram-err","", /* 14 */
  "disc","", /* 13 */
  "link-up","", /* 12 */
  "rcv-err","", /* 11 */
  "xmt-err","", /* 10 */
  "ssd-err","", /*  9 */
  "esd-err","", /*  8 */
  "ce-err","", /*  7 */
  "bcm-det","", /*  6 */
  "mdi-x-err","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "","", /*  2 */
  "","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_gige_status_ex_2(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "gige_status_ex_2((17 )", gige_status_ex_2_desc);
}

/* Error counts of various types saturate at 0xff */

CEXTERN uint16_t 
vsc8601_phy_read_rx_error_count(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 19);
}

CEXTERN uint16_t 
vsc8601_phy_read_false_carrier_count(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 20);
}

CEXTERN uint16_t 
vsc8601_phy_read_disconnect_count(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 21);
}

CEXTERN uint16_t 
vsc8601_phy_read_ex_crtl_set_1(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 23);
}

static char *ex_crtl_set_1_desc[16*2] = {
  "","", /* 15 */
  "","", /* 14 */
  "","", /* 13 */
  "","", /* 12 */
  "","", /* 11 */
  "","", /* 10 */
  "","", /*  9 */
  "skew-2ns-rx-tx","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "actiphy","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "","", /*  2 */
  "","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_ex_ctrl_set_1(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "ex_crtl_set_1   (23 )", ex_crtl_set_1_desc);
}

CEXTERN void  
vsc8601_phy_write_ex_crtl_set_1(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_main(unit, phy_addr, 23, reg);
}

CEXTERN void 
vsc8601_phy_rmw_ex_crtl_set_1(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_ex_crtl_set_1(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_ex_crtl_set_1(unit, phy_addr, reg);
}

CEXTERN uint16_t 
vsc8601_phy_read_ex_crtl_set_2(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 24);
}

CEXTERN void  
vsc8601_phy_write_ex_crtl_set_2(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_main(unit, phy_addr, 24, reg);
}

CEXTERN void 
vsc8601_phy_rmw_ex_crtl_set_2(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_ex_crtl_set_2(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_ex_crtl_set_2(unit, phy_addr, reg);
}

CEXTERN uint16_t  
vsc8601_phy_read_irq_msk(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 25);
}

CEXTERN void 
vsc8601_phy_write_irq_msk(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_main(unit, phy_addr, 25, reg);
}

CEXTERN uint16_t  
vsc8601_phy_read_irq_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 26);
}
static char *irq_status_desc[16*2] = {
  "pending","", /* 15 */
  "speed","", /* 14 */
  "link","", /* 13 */
  "fdx","", /* 12 */
  "auto-err","", /* 11 */
  "auto-cmpl","", /* 10 */
  "inl-pwr","", /*  9 */
  "","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "dwn-shft","", /*  2 */
  "ms-err","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_irq_status(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "irq_status      (26 )", irq_status_desc);
}

#if 0
/* RO */

CEXTERN uint16_t 
vsc8601_phy_read_aux_ctrl_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 28);
}

static char *aux_ctrl_status_desc[16*2] = {
  "auto-cmplt","", /* 15 */
  "auto-dis","", /* 14 */
  "cross-over","", /* 13 */
  "cd swap","", /* 12 */
  "a-pol","", /* 11 */
  "b-pol","", /* 10 */
  "c-pol","", /*  9 */
  "d-pol","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "fdx","", /*  5 */
  "gige","", /*  4 */
  "100-base-T","", /*  3 */
  "","", /*  2 */
  "sticky","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_aux_ctrl_status(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "aux_ctrl_status (28 )", aux_ctrl_status_desc);
}

CEXTERN uint16_t 
vsc8601_phy_read_delay_skew_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 29);
}

CEXTERN void 
vsc8601_phy_mii_print_delay_skew_status(uint16_t val)
{
  generic_printk(" delay_skew_     (29 )=%04x\n", val);
  generic_printk("    pair a delay: %02x\n", (val>>12)&7);
  generic_printk("    pair b delay: %02x\n", (val>> 8)&7);
  generic_printk("    pair c delay: %02x\n", (val>> 4)&7);