rt2860.h

Linux下的RT系列无线网卡驱动,可以直接在x86平台上编译

//
//
//  DMA RING DESCRIPTOR
//
#define E2PROM_CSR          0x0004
#define IO_CNTL_CSR         0x77d0

// 8051 firmware image - base address = 0x4000
#define FIRMWARE_IMAGE_BASE     0x2000
#define MAX_FIRMWARE_IMAGE_SIZE 8192    // 8kbyte

// TODO: ????? old RT2560 registers. to keep them or remove them?
//#define MCAST0                  0x0178  // multicast filter register 0
//#define MCAST1                  0x017c  // multicast filter register 1


// ================================================================
// Tx /	Rx / Mgmt ring descriptor definition
// ================================================================

// the following PID values are used to mark outgoing frame type in TXD->PID so that
// proper TX statistics can be collected based on these categories
// b3-2 of PID field -
#define PID_MGMT			0x05
#define PID_BEACON			0x0c
#define PID_DATA_NORMALUCAST	 	0x02
#define PID_DATA_AMPDU	 	0x04
#define PID_DATA_NO_ACK    	0x08
#define PID_DATA_NOT_NORM_ACK	 	0x03
// value domain of pTxD->HostQId (4-bit: 0~15)
#define QID_AC_BK               1   // meet ACI definition in 802.11e
#define QID_AC_BE               0   // meet ACI definition in 802.11e
#define QID_AC_VI               2
#define QID_AC_VO               3
#define QID_HCCA                4
#define NUM_OF_TX_RING          5
#define QID_MGMT                13
#define QID_RX                  14
#define QID_OTHER               15


// ------------------------------------------------------
// BBP & RF	definition
// ------------------------------------------------------
#define	BUSY		                1
#define	IDLE		                0

#define	BBP_R0					    0  // version
#define	BBP_R1				        1  // TSSI
#define	BBP_R2          			2  // TX configure
#define BBP_R3                      3
#define BBP_R4                      4
#define BBP_R5                      5
#define BBP_R6                      6
#define	BBP_R14			            14 // RX configure
#define BBP_R16                     16
#define BBP_R17                     17 // RX sensibility
#define BBP_R18                     18
#define BBP_R21                     21
#define BBP_R22                     22
#define BBP_R49                     49 //TSSI
#define BBP_R62                     62 // Rx SQ0 Threshold HIGH
#define BBP_R63                     63
#define BBP_R64                     64
#define BBP_R65                     65
#define BBP_R66                     66
#define BBP_R69                     69
#define BBP_R70                     70 // Rx AGC SQ CCK Xcorr threshold
#define BBP_R73                     73
#define BBP_R77                     77
#define BBP_R81                     81
#define BBP_R82                     82
#define BBP_R83                     83
#define BBP_R84                     84
#define BBP_R86						86
#define BBP_R94                     94 // Tx Gain Control
#define BBP_R105                    105
#define BBP_R113                    113
#define BBP_R114                    114
#define BBP_R115                    115
#define BBP_R116                    116
#define BBP_R117                    117
#define BBP_R118                    118
#define BBP_R119                    119
#define BBP_R120                    120
#define BBP_R121                    121
#define BBP_R122                    122
#define BBP_R123                    123


#define BBPR94_DEFAULT              0x06 // Add 1 value will gain 1db

//#define PHY_TR_SWITCH_TIME          5  // usec

//#define BBP_R17_LOW_SENSIBILITY     0x50
//#define BBP_R17_MID_SENSIBILITY     0x41
//#define BBP_R17_DYNAMIC_UP_BOUND    0x40
#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
#define RSSI_FOR_LOW_SENSIBILITY      -58
#define RSSI_FOR_MID_LOW_SENSIBILITY  -80
#define RSSI_FOR_MID_SENSIBILITY      -90

//-------------------------------------------------------------------------
// EEPROM definition
//-------------------------------------------------------------------------
#define EEDO                        0x08
#define EEDI                        0x04
#define EECS                        0x02
#define EESK                        0x01
#define EERL                        0x80

#define EEPROM_WRITE_OPCODE         0x05
#define EEPROM_READ_OPCODE          0x06
#define EEPROM_EWDS_OPCODE          0x10
#define EEPROM_EWEN_OPCODE          0x13

#define	NUM_EEPROM_BBP_PARMS		19			// Include NIC Config 0, 1, CR, TX ALC step, BBPs
#define	NUM_EEPROM_TX_G_PARMS		7
#define	EEPROM_NIC1_OFFSET		0x34		// The address is from NIC config 0, not BBP register ID
#define	EEPROM_NIC2_OFFSET		0x36		// The address is from NIC config 0, not BBP register ID
#define	EEPROM_BBP_BASE_OFFSET		0xf0		// The address is from NIC config 0, not BBP register ID
#define	EEPROM_G_TX_PWR_OFFSET		0x52
#define	EEPROM_G_TX2_PWR_OFFSET		0x60
#define EEPROM_LED1_OFFSET			0x3c
#define EEPROM_LED2_OFFSET			0x3e
#define EEPROM_LED3_OFFSET			0x40
#define EEPROM_LNA_OFFSET			0x44
#define EEPROM_A_TX_PWR_OFFSET      0x78
#define EEPROM_A_TX2_PWR_OFFSET      0xa6
//#define EEPROM_Japan_TX_PWR_OFFSET      0x90 // 802.11j
//#define EEPROM_Japan_TX2_PWR_OFFSET      0xbe
//#define EEPROM_TSSI_REF_OFFSET	0x54
//#define EEPROM_TSSI_DELTA_OFFSET	0x24
//#define EEPROM_CCK_TX_PWR_OFFSET  0x62
//#define EEPROM_CALIBRATE_OFFSET	0x7c
#define EEPROM_VERSION_OFFSET       0x02
#define	EEPROM_FREQ_OFFSET			0x3a
#define EEPROM_RSSI_BG_OFFSET		0x46
#define EEPROM_RSSI_A_OFFSET		0x4a
#define EEPROM_TXPOWER_BYRATE 	0xde	// 20MHZ power. 
#define EEPROM_TXPOWER_DELTA		0x50	// 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
#define VALID_EEPROM_VERSION        1

// PairKeyMode definition
#define PKMODE_NONE                 0
#define PKMODE_WEP64                1
#define PKMODE_WEP128               2
#define PKMODE_TKIP                 3
#define PKMODE_AES                  4
#define PKMODE_CKIP64               5
#define PKMODE_CKIP128              6
#define PKMODE_TKIP_NO_MIC          7       // MIC appended by driver: not a valid value in hardware key table

// =================================================================================
// WCID  format
// =================================================================================
//7.1	WCID  ENTRY  format  : 8bytes
typedef	struct	_WCID_ENTRY_STRUC {
	UCHAR		RXBABitmap7;    // bit0 for TID8, bit7 for TID 15
	UCHAR		RXBABitmap0;    // bit0 for TID0, bit7 for TID 7
	UCHAR		MAC[6];	// 0 for shared key table.  1 for pairwise key table
}	WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;

//8.1.1	SECURITY  KEY  format  : 8DW
// 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
typedef struct _HW_KEY_ENTRY {          // 32-byte per entry
    UCHAR   Key[16];
    UCHAR   TxMic[8];
    UCHAR   RxMic[8];
} HW_KEY_ENTRY, *PHW_KEY_ENTRY; 

//8.1.2	IV/EIV  format  : 2DW

//8.1.3	RX attribute entry format  : 1DW
#ifdef BIG_ENDIAN
typedef	struct	_MAC_ATTRIBUTE_STRUC {
	UINT32		rsv:22;
	UINT32		RXWIUDF:3;
	UINT32		BSSIDIdx:3; //multipleBSS index for the WCID
	UINT32		PairKeyMode:3;
	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
}	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
#else
typedef	struct	_MAC_ATTRIBUTE_STRUC {
	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
	UINT32		PairKeyMode:3;
	UINT32		BSSIDIdx:3; //multipleBSS index for the WCID
	UINT32		RXWIUDF:3;
	UINT32		rsv:22;
}	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
#endif


// =================================================================================
// TX / RX ring descriptor format
// =================================================================================

// the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
// MAC block use this TXINFO to control the transmission behavior of this frame.
#define TXINFO_SIZE                 0
#define FIFO_MGMT                 0
#define FIFO_HCCA                 1
#define FIFO_EDCA                 2

//
// TX descriptor format, Tx	ring, Mgmt Ring
//
#ifdef BIG_ENDIAN
typedef	struct	PACKED _TXD_STRUC {
	// Word 0
	UINT32		SDPtr0;
	// Word 1
	UINT32		DMADONE:1;
	UINT32		LastSec0:1;
	UINT32		SDLen0:14;
	UINT32		Burst:1;
	UINT32		LastSec1:1;
	UINT32		SDLen1:14;
	// Word 2
	UINT32		SDPtr1;
	// Word 3
	UINT32		ICO:1;	
	UINT32		UCO:1;	
	UINT32		TCO:1;	
	UINT32		rsv:2;
	UINT32		QSEL:2;	// select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
	UINT32		WIV:1;	// Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
	UINT32		rsv2:24;
}	TXD_STRUC, *PTXD_STRUC;
#else
typedef	struct	PACKED _TXD_STRUC {
	// Word	0
	UINT32		SDPtr0;
	// Word	1
	UINT32		SDLen1:14;
	UINT32		LastSec1:1;
	UINT32		Burst:1;
	UINT32		SDLen0:14;
	UINT32		LastSec0:1;
	UINT32		DMADONE:1;
	//Word2
	UINT32		SDPtr1;
	//Word3
	UINT32		rsv2:24;
	UINT32		WIV:1;	// Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
	UINT32		QSEL:2;	// select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
	UINT32		rsv:2;
	UINT32		TCO:1;	//  
	UINT32		UCO:1;	//  
	UINT32		ICO:1;	//
}	TXD_STRUC, *PTXD_STRUC;
#endif

//
// TXINFO
//
#ifdef BIG_ENDIAN
typedef	struct	_TXINFO_STRUC {
	// Word	0
	UINT32		USBDMATxburst:1;//used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint
	UINT32		USBDMANextVLD:1;	//used ONLY in USB bulk Aggregation, NextValid  
	UINT32		rsv1:3;
	UINT32		QSEL:2;	// select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
	UINT32		WIV:1;	// Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
	UINT32		rsv:8;
	UINT32		USBDMATxPktLen:16;	//used ONLY in USB bulk Aggregation,  Total byte counts of all sub-frame.
}	TXINFO_STRUC, *PTXINFO_STRUC;
#else
typedef	struct	_TXINFO_STRUC {
	// Word	0
	UINT32		USBDMATxPktLen:16;	//used ONLY in USB bulk Aggregation,  Total byte counts of all sub-frame.   
	UINT32		rsv:8;
	UINT32		WIV:1;	// Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
	UINT32		QSEL:2;	// select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
	UINT32		rsv1:3;
	UINT32		USBDMANextVLD:1;	//used ONLY in USB bulk Aggregation, NextValid  
	UINT32		USBDMATxburst:1;//used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint
}	TXINFO_STRUC, *PTXINFO_STRUC;
#endif
//
// TXD Wireless Information format for Tx ring and Mgmt Ring
//
//txop : for txop mode
// 0:txop for the MPDU frame will be handles by ASIC by register
// 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
#ifdef BIG_ENDIAN
typedef	struct	PACKED _TXWI_STRUC {
	// Word 0
	UINT32		PHYMODE:2;
	UINT32		rsv2:2;
	UINT32		Ifs:1;	// 
	UINT32		STBC:2;	//channel bandwidth 20MHz or 40 MHz
	UINT32		ShortGI:1;
	UINT32		BW:1;	//channel bandwidth 20MHz or 40 MHz
	UINT32		MCS:7;
	
	UINT32		rsv:6;
	UINT32		txop:2;	//tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
	UINT32		MpduDensity:3;
	UINT32		AMPDU:1;
	
	UINT32		TS:1;
	UINT32		CFACK:1;
	UINT32		MIMOps:1;	// the remote peer is in dynamic MIMO-PS mode
	UINT32		FRAG:1;		// 1 to inform TKIP engine this is a fragment.
	// Word 1
	UINT32		PacketId:4;
	UINT32		MPDUtotalByteCount:12;
	UINT32		WirelessCliID:8;
	UINT32		BAWinSize:6;
	UINT32		NSEQ:1;
	UINT32		ACK:1;
	// Word 2
	UINT32		IV;
	// Word 3
	UINT32		EIV;
}	TXWI_STRUC, *PTXWI_STRUC;
#else
typedef	struct	PACKED _TXWI_STRUC {
	// Word	0
	UINT32		FRAG:1;		// 1 to inform TKIP engine this is a fragment.
	UINT32		MIMOps:1;	// the remote peer is in dynamic MIMO-PS mode
	UINT32		CFACK:1;
	UINT32		TS:1;
		
	UINT32		AMPDU:1;
	UINT32		MpduDensity:3;
	UINT32		txop:2;	//FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
	UINT32		rsv:6;
	
	UINT32		MCS:7;
	UINT32		BW:1;	//channel bandwidth 20MHz or 40 MHz
	UINT32		ShortGI:1;
	UINT32		STBC:2;	// 1: STBC support MCS =0-7,   2,3 : RESERVE
	UINT32		Ifs:1;	// 
	UINT32		rsv2:2;	//channel bandwidth 20MHz or 40 MHz
	UINT32		PHYMODE:2;  
	// Word	1
	UINT32		ACK:1;
	UINT32		NSEQ:1;
	UINT32		BAWinSize:6;
	UINT32		WirelessCliID:8;
	UINT32		MPDUtotalByteCount:12;
	UINT32		PacketId:4;
	//Word2
	UINT32		IV;
	//Word3
	UINT32		EIV;
}	TXWI_STRUC, *PTXWI_STRUC;
#endif
//
// Rx descriptor format, Rx	Ring
//
#ifdef BIG_ENDIAN
typedef	struct	PACKED _RXD_STRUC	{
	// Word 0
	UINT32		SDP0;
	// Word 1
	UINT32		DDONE:1;
	UINT32		LS0:1;
	UINT32		SDL0:14;
	UINT32		Rsv:2;
	UINT32		SDL1:14;
	// Word 2
	UINT32		SDP1;
	// Word 3
	UINT32		Rsv1:13;
	UINT32		PlcpRssil:1;// To be moved
	UINT32		PlcpSignal:1;		// To be moved
	UINT32		Decrypted:1;	// this frame is being decrypted.
	UINT32		AMPDU:1;
	UINT32		L2PAD:1;
	UINT32		RSSI:1;
	UINT32		HTC:1;
	UINT32		AMSDU:1;		// rx with 802.3 header, not 802.11 header. obsolete.
	UINT32		CipherErr:2;        // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid	
	UINT32		Crc:1;              // 1: CRC error
	UINT32		MyBss:1;  	// 1: this frame belongs to the same BSSID
	UINT32		Bcast:1;            // 1: this is a broadcast frame	
	UINT32		Mcast:1;            // 1: this is a multicast frame
	UINT32		U2M:1;              // 1: this RX frame is unicast to me
	UINT32		FRAG:1;
	UINT32		NULLDATA:1;
	UINT32		DATA:1;
	UINT32		BA:1;
	
}	RXD_STRUC, *PRXD_STRUC;
#else
typedef	struct	PACKED _RXD_STRUC	{
	// Word	0
	UINT32		SDP0;
	// Word	1
	UINT32		SDL1:14;
	UINT32		Rsv:2;
	UINT32		SDL0:14;
	UINT32		LS0:1;
	UINT32		DDONE:1;
	// Word	2
	UINT32		SDP1;
	// Word	3
	UINT32		BA:1;
	UINT32		DATA:1;
	UINT32		NULLDATA:1;
	UINT32		FRAG:1;
	UINT32		U2M:1;              // 1: this RX frame is unicast to me
	UINT32		Mcast:1;            // 1: this is a multicast frame
	UINT32		Bcast:1;            // 1: this is a broadcast frame	
	UINT32		MyBss:1;  	// 1: this frame belongs to the same