📄 cstartup.lst
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288 00000000 0000001C
AT91C_PMC_PRES
EQU (0x7:SHL:2) ;- (PMC) Programmab
le Clock Prescaler
289 00000000 00000000
AT91C_PMC_PRES_CLK
EQU (0x0:SHL:2) ;- (PMC) Selected c
lock
290 00000000 00000004
AT91C_PMC_PRES_CLK_2
EQU (0x1:SHL:2) ;- (PMC) Selected c
lock divided by 2
291 00000000 00000008
AT91C_PMC_PRES_CLK_4
EQU (0x2:SHL:2) ;- (PMC) Selected c
lock divided by 4
292 00000000 0000000C
AT91C_PMC_PRES_CLK_8
EQU (0x3:SHL:2) ;- (PMC) Selected c
lock divided by 8
293 00000000 00000010
AT91C_PMC_PRES_CLK_16
EQU (0x4:SHL:2) ;- (PMC) Selected c
lock divided by 16
294 00000000 00000014
AT91C_PMC_PRES_CLK_32
EQU (0x5:SHL:2) ;- (PMC) Selected c
lock divided by 32
295 00000000 00000018
AT91C_PMC_PRES_CLK_64
EQU (0x6:SHL:2) ;- (PMC) Selected c
lock divided by 64
296 00000000 ;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable C
lock Register --------
297 00000000 ;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt E
nable Register --------
298 00000000 00000001
AT91C_PMC_MOSCS
EQU (0x1:SHL:0) ;- (PMC) MOSC Statu
s/Enable/Disable/Ma
ARM Macro Assembler Page 17
sk
299 00000000 00000004
AT91C_PMC_LOCK
EQU (0x1:SHL:2) ;- (PMC) PLL Status
/Enable/Disable/Mas
k
300 00000000 00000008
AT91C_PMC_MCKRDY
EQU (0x1:SHL:3) ;- (PMC) MCK_RDY St
atus/Enable/Disable
/Mask
301 00000000 00000100
AT91C_PMC_PCK0RDY
EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY S
tatus/Enable/Disabl
e/Mask
302 00000000 00000200
AT91C_PMC_PCK1RDY
EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY S
tatus/Enable/Disabl
e/Mask
303 00000000 00000400
AT91C_PMC_PCK2RDY
EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY
Status/Enable/Disab
le/Mask
304 00000000 ;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt D
isable Register --------
305 00000000 ;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Regis
ter --------
306 00000000 ;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt M
ask Register --------
307 00000000
308 00000000 ;- *****************************************************
************************
309 00000000 ;- SOFTWARE API DEFINITION FOR Reset Contr
oller Interface
310 00000000 ;- *****************************************************
************************
311 00000000 ^ 0 ;- AT91S_RSTC
312 00000000 00000000
RSTC_RCR
# 4 ;- Reset Control Re
gister
313 00000000 00000004
RSTC_RSR
# 4 ;- Reset Status Reg
ister
314 00000000 00000008
RSTC_RMR
# 4 ;- Reset Mode Regis
ter
315 00000000 ;- -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control
Register --------
316 00000000 00000001
AT91C_RSTC_PROCRST
EQU (0x1:SHL:0) ;- (RSTC) Processor
Reset
317 00000000 00000004
ARM Macro Assembler Page 18
AT91C_RSTC_PERRST
EQU (0x1:SHL:2) ;- (RSTC) Periphera
l Reset
318 00000000 00000008
AT91C_RSTC_EXTRST
EQU (0x1:SHL:3) ;- (RSTC) External
Reset
319 00000000 FF000000
AT91C_RSTC_KEY
EQU (0xFF:SHL:24)
;- (RSTC) Password
320 00000000 ;- -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status R
egister --------
321 00000000 00000001
AT91C_RSTC_URSTS
EQU (0x1:SHL:0) ;- (RSTC) User Rese
t Status
322 00000000 00000002
AT91C_RSTC_BODSTS
EQU (0x1:SHL:1) ;- (RSTC) Brownout
Detection Status
323 00000000 00000700
AT91C_RSTC_RSTTYP
EQU (0x7:SHL:8) ;- (RSTC) Reset Typ
e
324 00000000 00000000
AT91C_RSTC_RSTTYP_POWERUP
EQU (0x0:SHL:8) ;- (RSTC) Power-up
Reset. VDDCORE risi
ng.
325 00000000 00000100
AT91C_RSTC_RSTTYP_WAKEUP
EQU (0x1:SHL:8) ;- (RSTC) WakeUp Re
set. VDDCORE rising
.
326 00000000 00000200
AT91C_RSTC_RSTTYP_WATCHDOG
EQU (0x2:SHL:8) ;- (RSTC) Watchdog
Reset. Watchdog ove
rflow occured.
327 00000000 00000300
AT91C_RSTC_RSTTYP_SOFTWARE
EQU (0x3:SHL:8) ;- (RSTC) Software
Reset. Processor re
set required by the
software.
328 00000000 00000400
AT91C_RSTC_RSTTYP_USER
EQU (0x4:SHL:8) ;- (RSTC) User Rese
t. NRST pin detecte
d low.
329 00000000 00000500
AT91C_RSTC_RSTTYP_BROWNOUT
EQU (0x5:SHL:8) ;- (RSTC) Brownout
Reset occured.
330 00000000 00010000
AT91C_RSTC_NRSTL
EQU (0x1:SHL:16) ;- (RSTC) NRST pin
level
ARM Macro Assembler Page 19
331 00000000 00020000
AT91C_RSTC_SRCMP
EQU (0x1:SHL:17) ;- (RSTC) Software
Reset Command in P
rogress.
332 00000000 ;- -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Reg
ister --------
333 00000000 00000001
AT91C_RSTC_URSTEN
EQU (0x1:SHL:0) ;- (RSTC) User Rese
t Enable
334 00000000 00000010
AT91C_RSTC_URSTIEN
EQU (0x1:SHL:4) ;- (RSTC) User Rese
t Interrupt Enable
335 00000000 00000F00
AT91C_RSTC_ERSTL
EQU (0xF:SHL:8) ;- (RSTC) User Rese
t Enable
336 00000000 00010000
AT91C_RSTC_BODIEN
EQU (0x1:SHL:16) ;- (RSTC) Brownout
Detection Interrup
t Enable
337 00000000
338 00000000 ;- *****************************************************
************************
339 00000000 ;- SOFTWARE API DEFINITION FOR Real Time T
imer Controller Interface
340 00000000 ;- *****************************************************
************************
341 00000000 ^ 0 ;- AT91S_RTTC
342 00000000 00000000
RTTC_RTMR
# 4 ;- Real-time Mode R
egister
343 00000000 00000004
RTTC_RTAR
# 4 ;- Real-time Alarm
Register
344 00000000 00000008
RTTC_RTVR
# 4 ;- Real-time Value
Register
345 00000000 0000000C
RTTC_RTSR
# 4 ;- Real-time Status
Register
346 00000000 ;- -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mod
e Register --------
347 00000000 0000FFFF
AT91C_RTTC_RTPRES
EQU (0xFFFF:SHL:0) ;- (RTTC) Real-t
ime Timer Prescaler
Value
348 00000000 00010000
AT91C_RTTC_ALMIEN
EQU (0x1:SHL:16) ;- (RTTC) Alarm In
terrupt Enable
ARM Macro Assembler Page 20
349 00000000 00020000
AT91C_RTTC_RTTINCIEN
EQU (0x1:SHL:17) ;- (RTTC) Real Tim
e Timer Increment I
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