shub_mmr_t.h

来自「优龙2410linux2.6.8内核源代码」· C头文件 代码 · 共 1,825 行 · 第 1/5 页

/*                    Register "SH_NI0_LLP_CAPT_WD1"                    */
/*                    low order 64-bit captured word                    */
/* ==================================================================== */

typedef union sh_ni0_llp_capt_wd1_u {
	mmr_t	sh_ni0_llp_capt_wd1_regval;
	struct {
		mmr_t	data        : 64;
	} sh_ni0_llp_capt_wd1_s;
} sh_ni0_llp_capt_wd1_u_t;

/* ==================================================================== */
/*                    Register "SH_NI0_LLP_CAPT_WD2"                    */
/*                   high order 64-bit captured word                    */
/* ==================================================================== */

typedef union sh_ni0_llp_capt_wd2_u {
	mmr_t	sh_ni0_llp_capt_wd2_regval;
	struct {
		mmr_t	data        : 64;
	} sh_ni0_llp_capt_wd2_s;
} sh_ni0_llp_capt_wd2_u_t;

/* ==================================================================== */
/*                   Register "SH_NI0_LLP_CAPT_SBCB"                    */
/*                 captured sideband, sequence, and CRC                 */
/* ==================================================================== */

typedef union sh_ni0_llp_capt_sbcb_u {
	mmr_t	sh_ni0_llp_capt_sbcb_regval;
	struct {
		mmr_t	capturedrcvsbsn  : 16;
		mmr_t	capturedrcvcrc   : 16;
		mmr_t	sentallcberrors  : 1;
		mmr_t	sentallsnerrors  : 1;
		mmr_t	fakedallsnerrors : 1;
		mmr_t	chargeoverflow   : 1;
		mmr_t	chargeunderflow  : 1;
		mmr_t	reserved_0       : 27;
	} sh_ni0_llp_capt_sbcb_s;
} sh_ni0_llp_capt_sbcb_u_t;

/* ==================================================================== */
/*                      Register "SH_NI0_LLP_ERR"                       */
/* ==================================================================== */

typedef union sh_ni0_llp_err_u {
	mmr_t	sh_ni0_llp_err_regval;
	struct {
		mmr_t	rx_sn_err_count : 8;
		mmr_t	rx_cb_err_count : 8;
		mmr_t	retry_count     : 8;
		mmr_t	retry_timeout   : 1;
		mmr_t	rcv_link_reset  : 1;
		mmr_t	squash          : 1;
		mmr_t	power_not_ok    : 1;
		mmr_t	wire_cnt        : 24;
		mmr_t	wire_overflow   : 1;
		mmr_t	reserved_0      : 11;
	} sh_ni0_llp_err_s;
} sh_ni0_llp_err_u_t;

/* ==================================================================== */
/*                      Register "SH_NI1_LLP_STAT"                      */
/*               This register describes the LLP status.                */
/* ==================================================================== */

typedef union sh_ni1_llp_stat_u {
	mmr_t	sh_ni1_llp_stat_regval;
	struct {
		mmr_t	link_reset_state : 4;
		mmr_t	reserved_0       : 60;
	} sh_ni1_llp_stat_s;
} sh_ni1_llp_stat_u_t;

/* ==================================================================== */
/*                     Register "SH_NI1_LLP_RESET"                      */
/*           Writing issues a reset to the network interface            */
/* ==================================================================== */

typedef union sh_ni1_llp_reset_u {
	mmr_t	sh_ni1_llp_reset_regval;
	struct {
		mmr_t	link        : 1;
		mmr_t	warm        : 1;
		mmr_t	reserved_0  : 62;
	} sh_ni1_llp_reset_s;
} sh_ni1_llp_reset_u_t;

/* ==================================================================== */
/*                    Register "SH_NI1_LLP_RESET_EN"                    */
/*                 Controls LLP warm reset propagation                  */
/* ==================================================================== */

typedef union sh_ni1_llp_reset_en_u {
	mmr_t	sh_ni1_llp_reset_en_regval;
	struct {
		mmr_t	ok          : 1;
		mmr_t	reserved_0  : 63;
	} sh_ni1_llp_reset_en_s;
} sh_ni1_llp_reset_en_u_t;

/* ==================================================================== */
/*                   Register "SH_NI1_LLP_CHAN_MODE"                    */
/*              Sets the signaling mode of LLP and channel              */
/* ==================================================================== */

typedef union sh_ni1_llp_chan_mode_u {
	mmr_t	sh_ni1_llp_chan_mode_regval;
	struct {
		mmr_t	bitmode32         : 1;
		mmr_t	ac_encode         : 1;
		mmr_t	enable_tuning     : 1;
		mmr_t	enable_rmt_ft_upd : 1;
		mmr_t	enable_clkquad    : 1;
		mmr_t	reserved_0        : 59;
	} sh_ni1_llp_chan_mode_s;
} sh_ni1_llp_chan_mode_u_t;

/* ==================================================================== */
/*                     Register "SH_NI1_LLP_CONFIG"                     */
/*              Sets the configuration of LLP and channel               */
/* ==================================================================== */

typedef union sh_ni1_llp_config_u {
	mmr_t	sh_ni1_llp_config_regval;
	struct {
		mmr_t	maxburst    : 10;
		mmr_t	maxretry    : 10;
		mmr_t	nulltimeout : 6;
		mmr_t	ftu_time    : 12;
		mmr_t	reserved_0  : 26;
	} sh_ni1_llp_config_s;
} sh_ni1_llp_config_u_t;

/* ==================================================================== */
/*                    Register "SH_NI1_LLP_TEST_CTL"                    */
/* ==================================================================== */

typedef union sh_ni1_llp_test_ctl_u {
	mmr_t	sh_ni1_llp_test_ctl_regval;
	struct {
		mmr_t	pattern        : 40;
		mmr_t	send_test_mode : 2;
		mmr_t	reserved_0     : 2;
		mmr_t	wire_sel       : 6;
		mmr_t	reserved_1     : 2;
		mmr_t	lfsr_mode      : 2;
		mmr_t	noise_mode     : 2;
		mmr_t	armcapture     : 1;
		mmr_t	capturecbonly  : 1;
		mmr_t	sendcberror    : 1;
		mmr_t	sendsnerror    : 1;
		mmr_t	fakesnerror    : 1;
		mmr_t	captured       : 1;
		mmr_t	cberror        : 1;
		mmr_t	reserved_2     : 1;
	} sh_ni1_llp_test_ctl_s;
} sh_ni1_llp_test_ctl_u_t;

/* ==================================================================== */
/*                    Register "SH_NI1_LLP_CAPT_WD1"                    */
/*                    low order 64-bit captured word                    */
/* ==================================================================== */

typedef union sh_ni1_llp_capt_wd1_u {
	mmr_t	sh_ni1_llp_capt_wd1_regval;
	struct {
		mmr_t	data        : 64;
	} sh_ni1_llp_capt_wd1_s;
} sh_ni1_llp_capt_wd1_u_t;

/* ==================================================================== */
/*                    Register "SH_NI1_LLP_CAPT_WD2"                    */
/*                   high order 64-bit captured word                    */
/* ==================================================================== */

typedef union sh_ni1_llp_capt_wd2_u {
	mmr_t	sh_ni1_llp_capt_wd2_regval;
	struct {
		mmr_t	data        : 64;
	} sh_ni1_llp_capt_wd2_s;
} sh_ni1_llp_capt_wd2_u_t;

/* ==================================================================== */
/*                   Register "SH_NI1_LLP_CAPT_SBCB"                    */
/*                 captured sideband, sequence, and CRC                 */
/* ==================================================================== */

typedef union sh_ni1_llp_capt_sbcb_u {
	mmr_t	sh_ni1_llp_capt_sbcb_regval;
	struct {
		mmr_t	capturedrcvsbsn  : 16;
		mmr_t	capturedrcvcrc   : 16;
		mmr_t	sentallcberrors  : 1;
		mmr_t	sentallsnerrors  : 1;
		mmr_t	fakedallsnerrors : 1;
		mmr_t	chargeoverflow   : 1;
		mmr_t	chargeunderflow  : 1;
		mmr_t	reserved_0       : 27;
	} sh_ni1_llp_capt_sbcb_s;
} sh_ni1_llp_capt_sbcb_u_t;

/* ==================================================================== */
/*                      Register "SH_NI1_LLP_ERR"                       */
/* ==================================================================== */

typedef union sh_ni1_llp_err_u {
	mmr_t	sh_ni1_llp_err_regval;
	struct {
		mmr_t	rx_sn_err_count : 8;
		mmr_t	rx_cb_err_count : 8;
		mmr_t	retry_count     : 8;
		mmr_t	retry_timeout   : 1;
		mmr_t	rcv_link_reset  : 1;
		mmr_t	squash          : 1;
		mmr_t	power_not_ok    : 1;
		mmr_t	wire_cnt        : 24;
		mmr_t	wire_overflow   : 1;
		mmr_t	reserved_0      : 11;
	} sh_ni1_llp_err_s;
} sh_ni1_llp_err_u_t;

/* ==================================================================== */
/*                Register "SH_XNNI0_LLP_TO_FIFO02_FLOW"                */
/* ==================================================================== */

typedef union sh_xnni0_llp_to_fifo02_flow_u {
	mmr_t	sh_xnni0_llp_to_fifo02_flow_regval;
	struct {
		mmr_t	debit_vc0_withhold   : 6;
		mmr_t	reserved_0           : 1;
		mmr_t	debit_vc0_force_cred : 1;
		mmr_t	debit_vc2_withhold   : 6;
		mmr_t	reserved_1           : 1;
		mmr_t	debit_vc2_force_cred : 1;
		mmr_t	reserved_2           : 8;
		mmr_t	credit_vc0_dyn       : 6;
		mmr_t	reserved_3           : 2;
		mmr_t	credit_vc0_cap       : 6;
		mmr_t	reserved_4           : 10;
		mmr_t	credit_vc2_dyn       : 6;
		mmr_t	reserved_5           : 2;
		mmr_t	credit_vc2_cap       : 6;
		mmr_t	reserved_6           : 2;
	} sh_xnni0_llp_to_fifo02_flow_s;
} sh_xnni0_llp_to_fifo02_flow_u_t;

/* ==================================================================== */
/*                Register "SH_XNNI0_LLP_TO_FIFO13_FLOW"                */
/* ==================================================================== */

typedef union sh_xnni0_llp_to_fifo13_flow_u {
	mmr_t	sh_xnni0_llp_to_fifo13_flow_regval;
	struct {
		mmr_t	debit_vc0_withhold   : 6;
		mmr_t	reserved_0           : 1;
		mmr_t	debit_vc0_force_cred : 1;
		mmr_t	debit_vc2_withhold   : 6;
		mmr_t	reserved_1           : 1;
		mmr_t	debit_vc2_force_cred : 1;
		mmr_t	reserved_2           : 8;
		mmr_t	credit_vc0_dyn       : 6;
		mmr_t	reserved_3           : 2;
		mmr_t	credit_vc0_cap       : 6;
		mmr_t	reserved_4           : 10;
		mmr_t	credit_vc2_dyn       : 6;
		mmr_t	reserved_5           : 2;
		mmr_t	credit_vc2_cap       : 6;
		mmr_t	reserved_6           : 2;
	} sh_xnni0_llp_to_fifo13_flow_s;
} sh_xnni0_llp_to_fifo13_flow_u_t;

/* ==================================================================== */
/*                  Register "SH_XNNI0_LLP_DEBIT_FLOW"                  */
/* ==================================================================== */

typedef union sh_xnni0_llp_debit_flow_u {
	mmr_t	sh_xnni0_llp_debit_flow_regval;
	struct {
		mmr_t	debit_vc0_dyn : 5;
		mmr_t	reserved_0    : 3;
		mmr_t	debit_vc0_cap : 5;
		mmr_t	reserved_1    : 3;
		mmr_t	debit_vc1_dyn : 5;
		mmr_t	reserved_2    : 3;
		mmr_t	debit_vc1_cap : 5;
		mmr_t	reserved_3    : 3;
		mmr_t	debit_vc2_dyn : 5;
		mmr_t	reserved_4    : 3;
		mmr_t	debit_vc2_cap : 5;
		mmr_t	reserved_5    : 3;
		mmr_t	debit_vc3_dyn : 5;
		mmr_t	reserved_6    : 3;
		mmr_t	debit_vc3_cap : 5;
		mmr_t	reserved_7    : 3;
	} sh_xnni0_llp_debit_flow_s;
} sh_xnni0_llp_debit_flow_u_t;

/* ==================================================================== */
/*                   Register "SH_XNNI0_LINK_0_FLOW"                    */
/* ==================================================================== */

typedef union sh_xnni0_link_0_flow_u {
	mmr_t	sh_xnni0_link_0_flow_regval;
	struct {
		mmr_t	debit_vc0_withhold   : 6;
		mmr_t	reserved_0           : 1;
		mmr_t	debit_vc0_force_cred : 1;
		mmr_t	credit_vc0_test      : 7;
		mmr_t	reserved_1           : 1;
		mmr_t	credit_vc0_dyn       : 7;
		mmr_t	reserved_2           : 1;
		mmr_t	credit_vc0_cap       : 7;
		mmr_t	reserved_3           : 33;
	} sh_xnni0_link_0_flow_s;
} sh_xnni0_link_0_flow_u_t;

/* ==================================================================== */
/*                   Register "SH_XNNI0_LINK_1_FLOW"                    */
/* ==================================================================== */

typedef union sh_xnni0_link_1_flow_u {
	mmr_t	sh_xnni0_link_1_flow_regval;
	struct {
		mmr_t	debit_vc1_withhold   : 6;
		mmr_t	reserved_0           : 1;
		mmr_t	debit_vc1_force_cred : 1;
		mmr_t	credit_vc1_test      : 7;
		mmr_t	reserved_1           : 1;
		mmr_t	credit_vc1_dyn       : 7;
		mmr_t	reserved_2           : 1;
		mmr_t	credit_vc1_cap       : 7;
		mmr_t	reserved_3           : 33;
	} sh_xnni0_link_1_flow_s;
} sh_xnni0_link_1_flow_u_t;

/* ==================================================================== */
/*                   Register "SH_XNNI0_LINK_2_FLOW"                    */
/* ==================================================================== */

typedef union sh_xnni0_link_2_flow_u {
	mmr_t	sh_xnni0_link_2_flow_regval;
	struct {
		mmr_t	debit_vc2_withhold   : 6;
		mmr_t	reserved_0           : 1;
		mmr_t	debit_vc2_force_cred : 1;
		mmr_t	credit_vc2_test      : 7;
		mmr_t	reserved_1           : 1;
		mmr_t	credit_vc2_dyn       : 7;
		mmr_t	reserved_2           : 1;
		mmr_t	credit_vc2_cap       : 7;
		mmr_t	reserved_3           : 33;
	} sh_xnni0_link_2_flow_s;
} sh_xnni0_link_2_flow_u_t;

/* ==================================================================== */
/*                   Register "SH_XNNI0_LINK_3_FLOW"                    */
/* ==================================================================== */

typedef union sh_xnni0_link_3_flow_u {
	mmr_t	sh_xnni0_link_3_flow_regval;
	struct {
		mmr_t	debit_vc3_withhold   : 6;
		mmr_t	re