shub_mmr_t.h

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/*
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2001-2003 Silicon Graphics, Inc.  All rights reserved.
 */

#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H
#define _ASM_IA64_SN_SN2_SHUB_MMR_T_H

#include <asm/sn/arch.h>

/* ==================================================================== */
/*                   Register "SH_FSB_BINIT_CONTROL"                    */
/*                          FSB BINIT# Control                          */
/* ==================================================================== */

typedef union sh_fsb_binit_control_u {
	mmr_t	sh_fsb_binit_control_regval;
	struct {
		mmr_t	binit       : 1;
		mmr_t	reserved_0  : 63;
	} sh_fsb_binit_control_s;
} sh_fsb_binit_control_u_t;

/* ==================================================================== */
/*                   Register "SH_FSB_RESET_CONTROL"                    */
/*                          FSB Reset Control                           */
/* ==================================================================== */

typedef union sh_fsb_reset_control_u {
	mmr_t	sh_fsb_reset_control_regval;
	struct {
		mmr_t	reset       : 1;
		mmr_t	reserved_0  : 63;
	} sh_fsb_reset_control_s;
} sh_fsb_reset_control_u_t;

/* ==================================================================== */
/*                Register "SH_FSB_SYSTEM_AGENT_CONFIG"                 */
/*                    FSB System Agent Configuration                    */
/* ==================================================================== */

typedef union sh_fsb_system_agent_config_u {
	mmr_t	sh_fsb_system_agent_config_regval;
	struct {
		mmr_t	rcnt_scnt_en        : 1;
		mmr_t	reserved_0          : 2;
		mmr_t	berr_assert_en      : 1;
		mmr_t	berr_sampling_en    : 1;
		mmr_t	binit_assert_en     : 1;
		mmr_t	bnr_throttling_en   : 1;
		mmr_t	short_hang_en       : 1;
		mmr_t	inta_rsp_data       : 8;
		mmr_t	io_trans_rsp        : 1;
		mmr_t	xtpr_trans_rsp      : 1;
		mmr_t	inta_trans_rsp      : 1;
		mmr_t	reserved_1          : 4;
		mmr_t	tdot                : 1;
		mmr_t	serialize_fsb_en    : 1;
		mmr_t	reserved_2          : 7;
		mmr_t	binit_event_enables : 14;
		mmr_t	reserved_3          : 18;
	} sh_fsb_system_agent_config_s;
} sh_fsb_system_agent_config_u_t;

/* ==================================================================== */
/*                     Register "SH_FSB_VGA_REMAP"                      */
/*                     FSB VGA Address Space Remap                      */
/* ==================================================================== */

typedef union sh_fsb_vga_remap_u {
	mmr_t	sh_fsb_vga_remap_regval;
	struct {
		mmr_t	reserved_0            : 17;
		mmr_t	offset                : 19;
		mmr_t	asid                  : 2;
		mmr_t	nid                   : 11;
		mmr_t	reserved_1            : 13;
		mmr_t	vga_remapping_enabled : 1;
		mmr_t	reserved_2            : 1;
	} sh_fsb_vga_remap_s;
} sh_fsb_vga_remap_u_t;

/* ==================================================================== */
/*                    Register "SH_FSB_RESET_STATUS"                    */
/*                           FSB Reset Status                           */
/* ==================================================================== */

typedef union sh_fsb_reset_status_u {
	mmr_t	sh_fsb_reset_status_regval;
	struct {
		mmr_t	reset_in_progress : 1;
		mmr_t	reserved_0        : 63;
	} sh_fsb_reset_status_s;
} sh_fsb_reset_status_u_t;

/* ==================================================================== */
/*               Register "SH_FSB_SYMMETRIC_AGENT_STATUS"               */
/*                      FSB Symmetric Agent Status                      */
/* ==================================================================== */

typedef union sh_fsb_symmetric_agent_status_u {
	mmr_t	sh_fsb_symmetric_agent_status_regval;
	struct {
		mmr_t	cpu_0_active : 1;
		mmr_t	cpu_1_active : 1;
		mmr_t	cpus_ready   : 1;
		mmr_t	reserved_0   : 61;
	} sh_fsb_symmetric_agent_status_s;
} sh_fsb_symmetric_agent_status_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_CREDIT_COUNT_0"                   */
/*                Graphics-write Credit Count for CPU 0                 */
/* ==================================================================== */

typedef union sh_gfx_credit_count_0_u {
	mmr_t	sh_gfx_credit_count_0_regval;
	struct {
		mmr_t	count           : 20;
		mmr_t	reserved_0      : 43;
		mmr_t	reset_gfx_state : 1;
	} sh_gfx_credit_count_0_s;
} sh_gfx_credit_count_0_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_CREDIT_COUNT_1"                   */
/*                Graphics-write Credit Count for CPU 1                 */
/* ==================================================================== */

typedef union sh_gfx_credit_count_1_u {
	mmr_t	sh_gfx_credit_count_1_regval;
	struct {
		mmr_t	count           : 20;
		mmr_t	reserved_0      : 43;
		mmr_t	reset_gfx_state : 1;
	} sh_gfx_credit_count_1_s;
} sh_gfx_credit_count_1_u_t;

/* ==================================================================== */
/*                    Register "SH_GFX_MODE_CNTRL_0"                    */
/*         Graphics credit mode amd message ordering for CPU 0          */
/* ==================================================================== */

typedef union sh_gfx_mode_cntrl_0_u {
	mmr_t	sh_gfx_mode_cntrl_0_regval;
	struct {
		mmr_t	dword_credits      : 1;
		mmr_t	mixed_mode_credits : 1;
		mmr_t	relaxed_ordering   : 1;
		mmr_t	reserved_0         : 61;
	} sh_gfx_mode_cntrl_0_s;
} sh_gfx_mode_cntrl_0_u_t;

/* ==================================================================== */
/*                    Register "SH_GFX_MODE_CNTRL_1"                    */
/*         Graphics credit mode amd message ordering for CPU 1          */
/* ==================================================================== */

typedef union sh_gfx_mode_cntrl_1_u {
	mmr_t	sh_gfx_mode_cntrl_1_regval;
	struct {
		mmr_t	dword_credits      : 1;
		mmr_t	mixed_mode_credits : 1;
		mmr_t	relaxed_ordering   : 1;
		mmr_t	reserved_0         : 61;
	} sh_gfx_mode_cntrl_1_s;
} sh_gfx_mode_cntrl_1_u_t;

/* ==================================================================== */
/*                Register "SH_GFX_SKID_CREDIT_COUNT_0"                 */
/*              Graphics-write Skid Credit Count for CPU 0              */
/* ==================================================================== */

typedef union sh_gfx_skid_credit_count_0_u {
	mmr_t	sh_gfx_skid_credit_count_0_regval;
	struct {
		mmr_t	skid        : 20;
		mmr_t	reserved_0  : 44;
	} sh_gfx_skid_credit_count_0_s;
} sh_gfx_skid_credit_count_0_u_t;

/* ==================================================================== */
/*                Register "SH_GFX_SKID_CREDIT_COUNT_1"                 */
/*              Graphics-write Skid Credit Count for CPU 1              */
/* ==================================================================== */

typedef union sh_gfx_skid_credit_count_1_u {
	mmr_t	sh_gfx_skid_credit_count_1_regval;
	struct {
		mmr_t	skid        : 20;
		mmr_t	reserved_0  : 44;
	} sh_gfx_skid_credit_count_1_s;
} sh_gfx_skid_credit_count_1_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_STALL_LIMIT_0"                    */
/*                 Graphics-write Stall Limit for CPU 0                 */
/* ==================================================================== */

typedef union sh_gfx_stall_limit_0_u {
	mmr_t	sh_gfx_stall_limit_0_regval;
	struct {
		mmr_t	limit       : 26;
		mmr_t	reserved_0  : 38;
	} sh_gfx_stall_limit_0_s;
} sh_gfx_stall_limit_0_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_STALL_LIMIT_1"                    */
/*                 Graphics-write Stall Limit for CPU 1                 */
/* ==================================================================== */

typedef union sh_gfx_stall_limit_1_u {
	mmr_t	sh_gfx_stall_limit_1_regval;
	struct {
		mmr_t	limit       : 26;
		mmr_t	reserved_0  : 38;
	} sh_gfx_stall_limit_1_s;
} sh_gfx_stall_limit_1_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_STALL_TIMER_0"                    */
/*                 Graphics-write Stall Timer for CPU 0                 */
/* ==================================================================== */

typedef union sh_gfx_stall_timer_0_u {
	mmr_t	sh_gfx_stall_timer_0_regval;
	struct {
		mmr_t	timer_value : 26;
		mmr_t	reserved_0  : 38;
	} sh_gfx_stall_timer_0_s;
} sh_gfx_stall_timer_0_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_STALL_TIMER_1"                    */
/*                 Graphics-write Stall Timer for CPU 1                 */
/* ==================================================================== */

typedef union sh_gfx_stall_timer_1_u {
	mmr_t	sh_gfx_stall_timer_1_regval;
	struct {
		mmr_t	timer_value : 26;
		mmr_t	reserved_0  : 38;
	} sh_gfx_stall_timer_1_s;
} sh_gfx_stall_timer_1_u_t;

/* ==================================================================== */
/*                      Register "SH_GFX_WINDOW_0"                      */
/*                   Graphics-write Window for CPU 0                    */
/* ==================================================================== */

typedef union sh_gfx_window_0_u {
	mmr_t	sh_gfx_window_0_regval;
	struct {
		mmr_t	reserved_0    : 24;
		mmr_t	base_addr     : 12;
		mmr_t	reserved_1    : 27;
		mmr_t	gfx_window_en : 1;
	} sh_gfx_window_0_s;
} sh_gfx_window_0_u_t;

/* ==================================================================== */
/*                      Register "SH_GFX_WINDOW_1"                      */
/*                   Graphics-write Window for CPU 1                    */
/* ==================================================================== */

typedef union sh_gfx_window_1_u {
	mmr_t	sh_gfx_window_1_regval;
	struct {
		mmr_t	reserved_0    : 24;
		mmr_t	base_addr     : 12;
		mmr_t	reserved_1    : 27;
		mmr_t	gfx_window_en : 1;
	} sh_gfx_window_1_s;
} sh_gfx_window_1_u_t;

/* ==================================================================== */
/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0"               */
/*               Graphics-write Interrupt Limit for CPU 0               */
/* ==================================================================== */

typedef union sh_gfx_interrupt_timer_limit_0_u {
	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
	struct {
		mmr_t	interrupt_timer_limit : 8;
		mmr_t	reserved_0            : 56;
	} sh_gfx_interrupt_timer_limit_0_s;
} sh_gfx_interrupt_timer_limit_0_u_t;

/* ==================================================================== */
/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1"               */
/*               Graphics-write Interrupt Limit for CPU 1               */
/* ==================================================================== */

typedef union sh_gfx_interrupt_timer_limit_1_u {
	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
	struct {
		mmr_t	interrupt_timer_limit : 8;
		mmr_t	reserved_0            : 56;
	} sh_gfx_interrupt_timer_limit_1_s;
} sh_gfx_interrupt_timer_limit_1_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_WRITE_STATUS_0"                   */
/*                   Graphics Write Status for CPU 0                    */
/* ==================================================================== */

typedef union sh_gfx_write_status_0_u {
	mmr_t	sh_gfx_write_status_0_regval;
	struct {
		mmr_t	busy                : 1;
		mmr_t	reserved_0          : 62;
		mmr_t	re_enable_gfx_stall : 1;
	} sh_gfx_write_status_0_s;
} sh_gfx_write_status_0_u_t;

/* ==================================================================== */
/*                   Register "SH_GFX_WRITE_STATUS_1"                   */
/*                   Graphics Write Status for CPU 1                    */
/* ==================================================================== */

typedef union sh_gfx_write_status_1_u {
	mmr_t	sh_gfx_write_status_1_regval;
	struct {
		mmr_t	busy                : 1;
		mmr_t	reserved_0          : 62;
		mmr_t	re_enable_gfx_stall : 1;
	} sh_gfx_write_status_1_s;
} sh_gfx_write_status_1_u_t;

/* ==================================================================== */
/*                        Register "SH_II_INT0"                         */
/*                    SHub II Interrupt 0 Registers                     */
/* ==================================================================== */

typedef union sh_ii_int0_u {
	mmr_t	sh_ii_int0_regval;
	struct {
		mmr_t	idx         : 8;
		mmr_t	send        : 1;
		mmr_t	reserved_0  : 55;
	} sh_ii_int0_s;
} sh_ii_int0_u_t;

/* ==================================================================== */
/*                     Register "SH_II_INT0_CONFIG"                     */
/*                 SHub II Interrupt 0 Config Registers                 */
/* ==================================================================== */

typedef union sh_ii_int0_config_u {
	mmr_t	sh_ii_int0_config_regval;
	struct {
		mmr_t	type        : 3;
		mmr_t	agt         : 1;
		mmr_t	pid         : 16;
		mmr_t	reserved_0  : 1;
		mmr_t	base        : 29;
		mmr_t	reserved_1  : 14;
	} sh_ii_int0_config_s;
} sh_ii_int0_config_u_t;