pic.h

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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
 */
#ifndef _ASM_IA64_SN_PCI_PIC_H
#define _ASM_IA64_SN_PCI_PIC_H

/*
 * PIC AS DEVICE ZERO
 * ------------------
 *
 * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
 * be designated as 'device 0'.   That is a departure from earlier SGI
 * PCI bridges.  Because of that we use config space 1 to access the
 * config space of the first actual PCI device on the bus. 
 * Here's what the PIC manual says:
 *
 *     The current PCI-X bus specification now defines that the parent
 *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
 *     reduced the total number of devices from 8 to 4 and removed the
 *     device registers and windows, now only supporting devices 0,1,2, and
 *     3. PIC did leave all 8 configuration space windows. The reason was
 *     there was nothing to gain by removing them. Here in lies the problem.
 *     The device numbering we do using 0 through 3 is unrelated to the device
 *     numbering which PCI-X requires in configuration space. In the past we
 *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
 *     PCI-X requires we start a 1, not 0 and currently the PX brick
 *     does associate our:
 * 
 *         device 0 with configuration space window 1,
 *         device 1 with configuration space window 2, 
 *         device 2 with configuration space window 3,
 *         device 3 with configuration space window 4.
 *
 * The net effect is that all config space access are off-by-one with 
 * relation to other per-slot accesses on the PIC.   
 * Here is a table that shows some of that:
 *
 *                               Internal Slot#
 *           |
 *           |     0         1        2         3
 * ----------|---------------------------------------
 * config    |  0x21000   0x22000  0x23000   0x24000
 *           |
 * even rrb  |  0[0]      n/a      1[0]      n/a	[] == implied even/odd
 *           |
 * odd rrb   |  n/a       0[1]     n/a       1[1]
 *           |
 * int dev   |  00       01        10        11
 *           |
 * ext slot# |  1        2         3         4
 * ----------|---------------------------------------
 */


#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/sn/xtalk/xwidget.h>	/* generic widget header */
#else
#include <xtalk/xwidget.h>
#endif

#include <asm/sn/pci/pciio.h>


/*
 *    bus provider function table
 *
 *	Normally, this table is only handed off explicitly
 *	during provider initialization, and the PCI generic
 *	layer will stash a pointer to it in the vertex; however,
 *	exporting it explicitly enables a performance hack in
 *	the generic PCI provider where if we know at compile
 *	time that the only possible PCI provider is a
 *	pcibr, we can go directly to this ops table.
 */

extern pciio_provider_t pci_pic_provider;


/*
 * misc defines
 *
 */

#define PIC_WIDGET_PART_NUM_BUS0 0xd102
#define PIC_WIDGET_PART_NUM_BUS1 0xd112
#define PIC_WIDGET_MFGR_NUM 0x24
#define PIC_WIDGET_REV_A  0x1
#define PIC_WIDGET_REV_B  0x2
#define PIC_WIDGET_REV_C  0x3

#define PIC_XTALK_ADDR_MASK                     0x0000FFFFFFFFFFFF
#define PIC_INTERNAL_ATES                       1024


#define IS_PIC_PART_REV_A(rev) \
	((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_A)) || \
	(rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_A)))
#define IS_PIC_PART_REV_B(rev) \
        ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_B)) || \
        (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_B)))
#define IS_PIC_PART_REV_C(rev) \
        ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_C)) || \
        (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_C)))


/*
 * misc typedefs
 *
 */
typedef uint64_t picreg_t;
typedef uint64_t picate_t;

/*
 * PIC Bridge MMR defines
 */

/*
 * PIC STATUS register          offset 0x00000008
 */

#define PIC_STAT_PCIX_ACTIVE_SHFT       33

/*
 * PIC CONTROL register         offset 0x00000020
 */

#define PIC_CTRL_PCI_SPEED_SHFT         4
#define PIC_CTRL_PCI_SPEED              (0x3 << PIC_CTRL_PCI_SPEED_SHFT)
#define PIC_CTRL_PAGE_SIZE_SHFT         21
#define PIC_CTRL_PAGE_SIZE              (0x1 << PIC_CTRL_PAGE_SIZE_SHFT)


/*
 * PIC Intr Destination Addr    offset 0x00000038
 */

#define PIC_INTR_DEST_ADDR              0x0000FFFFFFFFFFFF
#define PIC_INTR_DEST_TID_SHFT          48
#define PIC_INTR_DEST_TID               (0xFull << PIC_INTR_DEST_TID_SHFT)

/*
 * PIC PCI Responce Buffer      offset 0x00000068
 */
#define PIC_RSP_BUF_ADDR                0x0000FFFFFFFFFFFF
#define PIC_RSP_BUF_NUM_SHFT            48
#define PIC_RSP_BUF_NUM                 (0xFull << PIC_RSP_BUF_NUM_SHFT)
#define PIC_RSP_BUF_DEV_NUM_SHFT        52
#define PIC_RSP_BUF_DEV_NUM             (0x3ull << PIC_RSP_BUF_DEV_NUM_SHFT)

/*
 * PIC PCI DIRECT MAP register  offset 0x00000080
 */
#define PIC_DIRMAP_DIROFF_SHFT          0
#define PIC_DIRMAP_DIROFF               (0x1FFFF << PIC_DIRMAP_DIROFF_SHFT)
#define PIC_DIRMAP_ADD512_SHFT          17
#define PIC_DIRMAP_ADD512               (0x1 << PIC_DIRMAP_ADD512_SHFT)
#define PIC_DIRMAP_WID_SHFT             20
#define PIC_DIRMAP_WID                  (0xF << PIC_DIRMAP_WID_SHFT)

#define PIC_DIRMAP_OFF_ADDRSHFT         31

/*
 * Interrupt Status register            offset 0x00000100
 */
#define PIC_ISR_PCIX_SPLIT_MSG_PE     (0x1ull << 45)
#define PIC_ISR_PCIX_SPLIT_EMSG       (0x1ull << 44)
#define PIC_ISR_PCIX_SPLIT_TO         (0x1ull << 43)
#define PIC_ISR_PCIX_UNEX_COMP        (0x1ull << 42)
#define PIC_ISR_INT_RAM_PERR          (0x1ull << 41)
#define PIC_ISR_PCIX_ARB_ERR          (0x1ull << 40)
#define PIC_ISR_PCIX_REQ_TOUT         (0x1ull << 39)
#define PIC_ISR_PCIX_TABORT           (0x1ull << 38)
#define PIC_ISR_PCIX_PERR             (0x1ull << 37)
#define PIC_ISR_PCIX_SERR             (0x1ull << 36)
#define PIC_ISR_PCIX_MRETRY           (0x1ull << 35)
#define PIC_ISR_PCIX_MTOUT            (0x1ull << 34)
#define PIC_ISR_PCIX_DA_PARITY        (0x1ull << 33)
#define PIC_ISR_PCIX_AD_PARITY        (0x1ull << 32)
#define PIC_ISR_PMU_PAGE_FAULT        (0x1ull << 30)
#define PIC_ISR_UNEXP_RESP            (0x1ull << 29)
#define PIC_ISR_BAD_XRESP_PKT         (0x1ull << 28)
#define PIC_ISR_BAD_XREQ_PKT          (0x1ull << 27)
#define PIC_ISR_RESP_XTLK_ERR         (0x1ull << 26)
#define PIC_ISR_REQ_XTLK_ERR          (0x1ull << 25)
#define PIC_ISR_INVLD_ADDR            (0x1ull << 24)
#define PIC_ISR_UNSUPPORTED_XOP       (0x1ull << 23)
#define PIC_ISR_XREQ_FIFO_OFLOW       (0x1ull << 22)
#define PIC_ISR_LLP_REC_SNERR         (0x1ull << 21)
#define PIC_ISR_LLP_REC_CBERR         (0x1ull << 20)
#define PIC_ISR_LLP_RCTY              (0x1ull << 19)
#define PIC_ISR_LLP_TX_RETRY          (0x1ull << 18)
#define PIC_ISR_LLP_TCTY              (0x1ull << 17)
#define PIC_ISR_PCI_ABORT             (0x1ull << 15)
#define PIC_ISR_PCI_PARITY            (0x1ull << 14)
#define PIC_ISR_PCI_SERR              (0x1ull << 13)
#define PIC_ISR_PCI_PERR              (0x1ull << 12)
#define PIC_ISR_PCI_MST_TIMEOUT       (0x1ull << 11)
#define PIC_ISR_PCI_RETRY_CNT         (0x1ull << 10)
#define PIC_ISR_XREAD_REQ_TIMEOUT     (0x1ull << 9)
#define PIC_ISR_INT_MSK               (0xffull << 0)
#define PIC_ISR_INT(x)                (0x1ull << (x))

#define PIC_ISR_LINK_ERROR            \
                (PIC_ISR_LLP_REC_SNERR|PIC_ISR_LLP_REC_CBERR|       \
                 PIC_ISR_LLP_RCTY|PIC_ISR_LLP_TX_RETRY|             \
                 PIC_ISR_LLP_TCTY)

#define PIC_ISR_PCIBUS_PIOERR         \
                (PIC_ISR_PCI_MST_TIMEOUT|PIC_ISR_PCI_ABORT|         \
                 PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT)

#define PIC_ISR_PCIBUS_ERROR          \
                (PIC_ISR_PCIBUS_PIOERR|PIC_ISR_PCI_PERR|            \
                 PIC_ISR_PCI_SERR|PIC_ISR_PCI_RETRY_CNT|            \
                 PIC_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR|              \
                 PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY|             \
                 PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY|     \
                 PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP|      \
                 PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG|     \
                 PIC_ISR_PCIX_SPLIT_MSG_PE)