pcibr.h

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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
 */
#ifndef _ASM_IA64_SN_PCI_PCIBR_H
#define _ASM_IA64_SN_PCI_PCIBR_H

#if defined(__KERNEL__)

#include <linux/config.h>
#include <asm/sn/dmamap.h>
#include <asm/sn/driver.h>
#include <asm/sn/pio.h>

#include <asm/sn/pci/pciio.h>
#include <asm/sn/pci/bridge.h>

/* =====================================================================
 *    symbolic constants used by pcibr's xtalk bus provider
 */

#define PCIBR_PIOMAP_BUSY		0x80000000

#define PCIBR_DMAMAP_BUSY		0x80000000
#define	PCIBR_DMAMAP_SSRAM		0x40000000

#define PCIBR_INTR_BLOCKED		0x40000000
#define PCIBR_INTR_BUSY			0x80000000

#ifndef __ASSEMBLY__

/* =====================================================================
 *    opaque types used by pcibr's xtalk bus provider
 */

typedef struct pcibr_piomap_s *pcibr_piomap_t;
typedef struct pcibr_dmamap_s *pcibr_dmamap_t;
typedef struct pcibr_intr_s *pcibr_intr_t;

/* =====================================================================
 *    bus provider function table
 *
 *	Normally, this table is only handed off explicitly
 *	during provider initialization, and the PCI generic
 *	layer will stash a pointer to it in the vertex; however,
 *	exporting it explicitly enables a performance hack in
 *	the generic PCI provider where if we know at compile
 *	time that the only possible PCI provider is a
 *	pcibr, we can go directly to this ops table.
 */

extern pciio_provider_t pci_pic_provider;

/* =====================================================================
 *    secondary entry points: pcibr PCI bus provider
 *
 *	These functions are normally exported explicitly by
 *	a direct call from the pcibr initialization routine
 *	into the generic crosstalk provider; they are included
 *	here to enable a more aggressive performance hack in
 *	the generic crosstalk layer, where if we know that the
 *	only possible crosstalk provider is pcibr, and we can
 *	guarantee that all entry points are properly named, and
 *	we can deal with the implicit casting properly, then
 *	we can turn many of the generic provider routines into
 *	plain brances, or even eliminate them (given sufficient
 *	smarts on the part of the compilation system).
 */

extern pcibr_piomap_t	pcibr_piomap_alloc(vertex_hdl_t dev,
					   device_desc_t dev_desc,
					   pciio_space_t space,
					   iopaddr_t pci_addr,
					   size_t byte_count,
					   size_t byte_count_max,
					   unsigned flags);

extern void		pcibr_piomap_free(pcibr_piomap_t piomap);

extern caddr_t		pcibr_piomap_addr(pcibr_piomap_t piomap,
					  iopaddr_t xtalk_addr,
					  size_t byte_count);

extern void		pcibr_piomap_done(pcibr_piomap_t piomap);

extern int		pcibr_piomap_probe(pcibr_piomap_t piomap,
					   off_t offset,
					   int len,
					   void *valp);

extern caddr_t		pcibr_piotrans_addr(vertex_hdl_t dev,
					    device_desc_t dev_desc,
					    pciio_space_t space,
					    iopaddr_t pci_addr,
					    size_t byte_count,
					    unsigned flags);

extern iopaddr_t	pcibr_piospace_alloc(vertex_hdl_t dev,
					     device_desc_t dev_desc,
					     pciio_space_t space,
					     size_t byte_count,
					     size_t alignment);
extern void		pcibr_piospace_free(vertex_hdl_t dev,
					    pciio_space_t space,
					    iopaddr_t pciaddr,
					    size_t byte_count);

extern pcibr_dmamap_t	pcibr_dmamap_alloc(vertex_hdl_t dev,
					   device_desc_t dev_desc,
					   size_t byte_count_max,
					   unsigned flags);

extern void		pcibr_dmamap_free(pcibr_dmamap_t dmamap);

extern iopaddr_t	pcibr_dmamap_addr(pcibr_dmamap_t dmamap,
					  paddr_t paddr,
					  size_t byte_count);

extern void		pcibr_dmamap_done(pcibr_dmamap_t dmamap);

/*
 * pcibr_get_dmatrans_node() will return the compact node id to which  
 * all 32-bit Direct Mapping memory accesses will be directed.
 * (This node id can be different for each PCI bus.) 
 */

extern cnodeid_t	pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl);

extern iopaddr_t	pcibr_dmatrans_addr(vertex_hdl_t dev,
					    device_desc_t dev_desc,
					    paddr_t paddr,
					    size_t byte_count,
					    unsigned flags);

extern void		pcibr_dmamap_drain(pcibr_dmamap_t map);

extern void		pcibr_dmaaddr_drain(vertex_hdl_t vhdl,
					    paddr_t addr,
					    size_t bytes);

typedef unsigned	pcibr_intr_ibit_f(pciio_info_t info,
					  pciio_intr_line_t lines);

extern void		pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *);

extern pcibr_intr_t	pcibr_intr_alloc(vertex_hdl_t dev,
					 device_desc_t dev_desc,
					 pciio_intr_line_t lines,
					 vertex_hdl_t owner_dev);

extern void		pcibr_intr_free(pcibr_intr_t intr);

extern int		pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t);

extern void		pcibr_intr_disconnect(pcibr_intr_t intr);

extern vertex_hdl_t	pcibr_intr_cpu_get(pcibr_intr_t intr);

extern void		pcibr_provider_startup(vertex_hdl_t pcibr);

extern void		pcibr_provider_shutdown(vertex_hdl_t pcibr);

extern int		pcibr_reset(vertex_hdl_t dev);

extern pciio_endian_t	pcibr_endian_set(vertex_hdl_t dev,
					 pciio_endian_t device_end,
					 pciio_endian_t desired_end);

extern uint64_t		pcibr_config_get(vertex_hdl_t conn,
					 unsigned reg,
					 unsigned size);

extern void		pcibr_config_set(vertex_hdl_t conn,
					 unsigned reg,
					 unsigned size,
					 uint64_t value);

extern pciio_slot_t	pcibr_error_extract(vertex_hdl_t pcibr_vhdl,
					    pciio_space_t *spacep,
					    iopaddr_t *addrp);

extern int		pcibr_wrb_flush(vertex_hdl_t pconn_vhdl);
extern int		pcibr_rrb_check(vertex_hdl_t pconn_vhdl,
					int *count_vchan0,
					int *count_vchan1,
					int *count_reserved,
					int *count_pool);

extern int		pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd,
					     int dev_1_rrbs, int virt1,
					     int dev_2_rrbs, int virt2,
					     int dev_3_rrbs, int virt3,
					     int dev_4_rrbs, int virt4);

typedef void
rrb_alloc_funct_f	(vertex_hdl_t xconn_vhdl,
			 int *vendor_list);

typedef rrb_alloc_funct_f      *rrb_alloc_funct_t;

void			pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl,
					       rrb_alloc_funct_f *func);

extern int		pcibr_device_unregister(vertex_hdl_t);
extern void             pcibr_driver_reg_callback(vertex_hdl_t, int, int, int);
extern void             pcibr_driver_unreg_callback(vertex_hdl_t,
                                                    int, int, int);


extern void *		pcibr_bridge_ptr_get(vertex_hdl_t, int);

/*
 * Bridge-specific flags that can be set via pcibr_device_flags_set
 * and cleared via pcibr_device_flags_clear.  Other flags are
 * more generic and are maniuplated through PCI-generic interfaces.
 *
 * Note that all PCI implementation-specific flags (Bridge flags, in
 * this case) are in bits 15-31.  The lower 15 bits are reserved
 * for PCI-generic flags.
 *
 * Some of these flags have been "promoted" to the
 * generic layer, so they can be used without having
 * to "know" that the PCI bus is hosted by a Bridge.
 *
 * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when 
 * allocating ATE's. ATE count computation will assume that the
 * address to be mapped will start on a page boundary.
 */
#define PCIBR_NO_ATE_ROUNDUP    0x00008000
#define PCIBR_WRITE_GATHER	0x00010000	/* please use PCIIO version */
#define PCIBR_NOWRITE_GATHER	0x00020000	/* please use PCIIO version */
#define PCIBR_PREFETCH		0x00040000	/* please use PCIIO version */
#define PCIBR_NOPREFETCH	0x00080000	/* please use PCIIO version */
#define PCIBR_PRECISE		0x00100000
#define PCIBR_NOPRECISE		0x00200000
#define PCIBR_BARRIER		0x00400000
#define PCIBR_NOBARRIER		0x00800000
#define PCIBR_VCHAN0		0x01000000
#define PCIBR_VCHAN1		0x02000000
#define PCIBR_64BIT		0x04000000
#define PCIBR_NO64BIT		0x08000000
#define PCIBR_SWAP		0x10000000
#define PCIBR_NOSWAP		0x20000000

#define	PCIBR_EXTERNAL_ATES	0x40000000	/* uses external ATEs */
#define	PCIBR_ACTIVE		0x80000000	/* need a "done" */

/* Flags that have meaning to pcibr_device_flags_{set,clear} */
#define PCIBR_DEVICE_FLAGS (	\
	PCIBR_WRITE_GATHER	|\
	PCIBR_NOWRITE_GATHER	|\
	PCIBR_PREFETCH		|\
	PCIBR_NOPREFETCH	|\
	PCIBR_PRECISE		|\
	PCIBR_NOPRECISE		|\
	PCIBR_BARRIER		|\
	PCIBR_NOBARRIER		\
)

/* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */
#define PCIBR_DMA_FLAGS (	\
	PCIBR_PREFETCH		|\
	PCIBR_NOPREFETCH	|\
	PCIBR_PRECISE		|\
	PCIBR_NOPRECISE		|\