pcibr_private.h

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	 */
	uint64_t		bss_device;

	/* Number of sets on GBR/REALTIME bit outstanding
	 * Used by Priority I/O for tracking reservations
	 */
	int                     bss_pri_uctr;

	/* Number of "uses" of PMU, 32-bit direct,
	 * and 64-bit direct DMA (0:none, <0: trans,
	 * >0: how many dmamaps). Device(x) bits
	 * controlling attribute of each kind of
	 * channel can't be changed by dmamap_alloc
	 * or dmatrans if the controlling counter
	 * is nonzero. dmatrans is forever.
	 */
	int                     bss_pmu_uctr;
	int                     bss_d32_uctr;
	int                     bss_d64_uctr;

	/* When the contents of mapping configuration
	 * information is locked down by dmatrans,
	 * repeated checks of the same flags should
	 * be shortcircuited for efficiency.
	 */
	iopaddr_t		bss_d64_base;
	unsigned		bss_d64_flags;
	iopaddr_t		bss_d32_base;
	unsigned		bss_d32_flags;
    } bs_slot[8];

    pcibr_intr_bits_f	       *bs_intr_bits;

    /* PIC PCI-X Read Buffer Management :
     * bs_pcix_num_funcs: the total number of PCI-X functions
     *  on the bus
     * bs_pcix_split_tot: total number of outstanding split
     *  transactions requested by all functions on the bus
     * bs_pcix_rbar_percent_allowed: the percentage of the
     *  total number of buffers a function requested that are 
     *  available to it, not including the 1 RBAR guaranteed 
     *  to it.
     * bs_pcix_rbar_inuse: number of RBARs in use.
     * bs_pcix_rbar_avail: number of RBARs available.  NOTE:
     *  this value can go negative if we oversubscribe the 
     *  RBARs.  (i.e.  We have 16 RBARs but 17 functions).
     */
    int			    bs_pcix_num_funcs;
    int			    bs_pcix_split_tot;
    int			    bs_pcix_rbar_percent_allowed;

    int			    bs_pcix_rbar_inuse;
    int			    bs_pcix_rbar_avail;


    /* RRB MANAGEMENT
     * bs_rrb_fixed: bitmap of slots whose RRB
     *	allocations we should not "automatically" change
     * bs_rrb_avail: number of RRBs that have not
     *  been allocated or reserved for {even,odd} slots
     * bs_rrb_res: number of RRBs currently reserved for the
     *	use of the index slot number
     * bs_rrb_res_dflt: number of RRBs reserved at boot
     *  time for the use of the index slot number
     * bs_rrb_valid: number of RRBs currently marked valid
     *	for the indexed slot/vchan number; array[slot][vchan]
     * bs_rrb_valid_dflt: number of RRBs marked valid at boot
     *  time for the indexed slot/vchan number; array[slot][vchan]
     */
    int                     bs_rrb_fixed;
    int			    bs_rrb_avail[2];
    int			    bs_rrb_res[8];
    int			    bs_rrb_res_dflt[8];
    int			    bs_rrb_valid[8][4];
    int			    bs_rrb_valid_dflt[8][4];
    struct {
	/* Each Bridge interrupt bit has a single XIO
	 * interrupt channel allocated.
	 */
	xtalk_intr_t            bsi_xtalk_intr;
	/*
	 * A wrapper structure is associated with each
	 * Bridge interrupt bit.
	 */
	struct pcibr_intr_wrap_s  bsi_pcibr_intr_wrap;
	/* The bus and interrupt bit, used for pcibr_setpciint().
	 * The pci busnum is bit3, int_bits bit2:0
	 */
	uint32_t		bsi_int_bit;

    } bs_intr[8];

    xtalk_intr_t		bsi_err_intr;

    /*
     * We stash away some information in this structure on getting
     * an error interrupt. This information is used during PIO read/
     * write error handling.
     *
     * As it stands now, we do not re-enable the error interrupt
     * till the error is resolved. Error resolution happens either at
     * bus error time for PIO Read errors (~100 microseconds), or at
     * the scheduled timeout time for PIO write errors (~milliseconds).
     * If this delay causes problems, we may need to move towards
     * a different scheme..
     *
     * Note that there is no locking while looking at this data structure.
     * There should not be any race between bus error code and
     * error interrupt code.. will look into this if needed.
     *
     * NOTE: The above discussion of error interrupt processing is
     *       no longer true. Whether it should again be true, is
     *       being looked into.
     */
    struct br_errintr_info {
	int                     bserr_toutcnt;
	iopaddr_t               bserr_addr;	/* Address where error occured */
	uint64_t		bserr_intstat;	/* interrupts active at error dump */
    } bs_errinfo;

    /*
     * PCI Bus Space allocation data structure.
     *
     * The resource mapping functions rmalloc() and rmfree() are used
     * to manage the PCI bus I/O, small window, and memory  address 
     * spaces.
     *
     * This info is used to assign PCI bus space addresses to cards
     * via their BARs and to the callers of the pcibr_piospace_alloc()
     * interface.
     *
     * Users of the pcibr_piospace_alloc() interface, such as the VME
     * Universe chip, need PCI bus space that is not acquired by BARs.
     * Most of these users need "large" amounts of PIO space (typically
     * in Megabytes), and they generally tend to take once and never
     * release. 
     */
    struct pciio_win_map_s	bs_io_win_map;	/* I/O addr space */
    struct pciio_win_map_s	bs_swin_map;	/* Small window addr space */
    struct pciio_win_map_s	bs_mem_win_map;	/* Memory addr space */

    struct resource		bs_io_win_root_resource; /* I/O addr space */
    struct resource		bs_swin_root_resource; /* Small window addr space */
    struct resource		bs_mem_win_root_resource; /* Memory addr space */

    int                   bs_bus_addr_status;    /* Bus space status */

#define PCIBR_BUS_ADDR_MEM_FREED       1  /* Reserved PROM mem addr freed */
#define PCIBR_BUS_ADDR_IO_FREED        2  /* Reserved PROM I/O addr freed */

    struct bs_errintr_stat_s {
	uint32_t		bs_errcount_total;
	uint32_t		bs_lasterr_timestamp;
	uint32_t		bs_lasterr_snapshot;
    } bs_errintr_stat[PCIBR_ISR_MAX_ERRS];

    /*
     * Bridge-wide endianness control for
     * large-window PIO mappings
     *
     * These fields are set to PCIIO_BYTE_SWAP
     * or PCIIO_WORD_VALUES once the swapper
     * has been configured, one way or the other,
     * for the direct windows. If they are zero,
     * nobody has a PIO mapping through that window,
     * and the swapper can be set either way.
     */
    unsigned		bs_pio_end_io;
    unsigned		bs_pio_end_mem;
};

#define	PCIBR_ERRTIME_THRESHOLD		(100)
#define	PCIBR_ERRRATE_THRESHOLD		(100)

/*
 * pcibr will respond to hints dropped in its vertex
 * using the following structure.
 */
struct pcibr_hints_s {
    /* ph_host_slot is actually +1 so "0" means "no host" */
    pciio_slot_t            ph_host_slot[8];	/* REQ/GNT/INT in use by ... */
    unsigned int            ph_rrb_fixed;	/* do not change RRB allocations */
    unsigned int            ph_hands_off;	/* prevent further pcibr operations */
    rrb_alloc_funct_t       rrb_alloc_funct;	/* do dynamic rrb allocation */
    pcibr_intr_bits_f	   *ph_intr_bits;	/* map PCI INT[ABCD] to Bridge Int(n) */
};

/*
 * Number of bridge non-fatal error interrupts we can see before
 * we decide to disable that interrupt.
 */
#define	PCIBR_ERRINTR_DISABLE_LEVEL	10000

/* =====================================================================
 *    Bridge (pcibr) state management functions
 *
 *      pcibr_soft_get is here because we do it in a lot
 *      of places and I want to make sure they all stay
 *      in step with each other.
 *
 *      pcibr_soft_set is here because I want it to be
 *      closely associated with pcibr_soft_get, even
 *      though it is only called in one place.
 */

#define pcibr_soft_get(v)       ((pcibr_soft_t)hwgraph_fastinfo_get((v)))
#define pcibr_soft_set(v,i)     (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i)))

/*
 * Additional PIO spaces per slot are
 * recorded in this structure.
 */
struct pciio_piospace_s {
    pciio_piospace_t        next;	/* another space for this device */
    char                    free;	/* 1 if free, 0 if in use */
    pciio_space_t           space;	/* Which space is in use */
    iopaddr_t               start;	/* Starting address of the PIO space */
    size_t                  count;	/* size of PIO space */
};

/* 
 * pcibr_soft structure locking macros
 */
inline static unsigned long
pcibr_lock(pcibr_soft_t pcibr_soft)
{
        unsigned long flag;
        spin_lock_irqsave(&pcibr_soft->bs_lock, flag);
        return(flag);
}
#define pcibr_unlock(pcibr_soft, flag)  spin_unlock_irqrestore(&pcibr_soft->bs_lock, flag)

#define PCIBR_VALID_SLOT(ps, s)     (s < PCIBR_NUM_SLOTS(ps))
#define PCIBR_D64_BASE_UNSET    (0xFFFFFFFFFFFFFFFF)
#define PCIBR_D32_BASE_UNSET    (0xFFFFFFFF)
#define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev"

#define PCIBR_SOFT_LIST 1
#if PCIBR_SOFT_LIST
typedef struct pcibr_list_s *pcibr_list_p;
struct pcibr_list_s {
    pcibr_list_p            bl_next;
    pcibr_soft_t            bl_soft;
    vertex_hdl_t            bl_vhdl;
};
#endif /* PCIBR_SOFT_LIST */

/* Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot. */
#define DEV_PER_WIDGET (2*2*8)

struct sn_flush_device_list {
	int bus;
	int slot;
	int pin;
	struct bar_list {
		unsigned long start;
		unsigned long end;
	} bar_list[PCI_ROM_RESOURCE];
	unsigned long force_int_addr;
	volatile unsigned long flush_addr;
	spinlock_t flush_lock;
};

struct sn_flush_nasid_entry  {
        struct sn_flush_device_list **widget_p;
        unsigned long        iio_itte[8];
};

#endif				/* _ASM_SN_PCI_PCIBR_PRIVATE_H */