pcibr_private.h

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#define	bi_arg		bi_pi.pi_arg	/* handler parameter (when connected) */
#define bi_mustruncpu	bi_pi.pi_mustruncpu /* Where we must run. */
#define bi_irq		bi_pi.pi_irq	/* IRQ assigned. */
#define bi_cpu		bi_pi.pi_cpu	/* cpu assigned. */
    unsigned int                bi_ibits;	/* which Bridge interrupt bit(s) */
    pcibr_soft_t            bi_soft;	/* shortcut to soft info */
    struct pcibr_intr_cbuf_s bi_ibuf;	/* circular buffer of wrap ptrs */
    unsigned		bi_last_intr;	/* For Shub lb lost intr. bug */
};


/* 
 * PCIBR_INFO_SLOT_GET_EXT returns the external slot number that the card
 * resides in.  (i.e the slot number silk screened on the back of the I/O 
 * brick).  PCIBR_INFO_SLOT_GET_INT returns the internal slot (or device)
 * number used by the pcibr code to represent that external slot (i.e to 
 * set bit patterns in BRIDGE/PIC registers to represent the device, or to
 * offset into an array, or ...).
 *
 * In BRIDGE and XBRIDGE the external slot and internal device numbering 
 * are the same.  (0->0, 1->1, 2->2,... 7->7)  BUT in the PIC the external
 * slot number is always 1 greater than the internal device number (1->0, 
 * 2->1, 3->2, 4->3).  This is due to the fact that the PCI-X spec requires
 * that the 'bridge' (i.e PIC) be designated as 'device 0', thus external
 * slot numbering can't start at zero.
 *
 * PCIBR_DEVICE_TO_SLOT converts an internal device number to an external
 * slot number.  NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE.
 *
 * PCIBR_SLOT_TO_DEVICE converts an external slot number to an internal
 * device number.  NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE.
 */
#define PCIBR_INFO_SLOT_GET_EXT(info)	    (((pcibr_info_t)info)->f_slot)
#define PCIBR_INFO_SLOT_GET_INT(info)	    (((pcibr_info_t)info)->f_dev)

#define PCIBR_DEVICE_TO_SLOT(pcibr_soft, dev_num) \
	(((dev_num) != PCIIO_SLOT_NONE) ? ((dev_num) + 1) : PCIIO_SLOT_NONE)

#define PCIBR_SLOT_TO_DEVICE(pcibr_soft, slot) \
        (((slot) != PCIIO_SLOT_NONE) ? ((slot) - 1) : PCIIO_SLOT_NONE)

/*
 * per-connect point pcibr data, including standard pciio data in-line:
 */
struct pcibr_info_s {
    struct pciio_info_s	    f_c;	/* MUST BE FIRST. */
#define	f_vertex	f_c.c_vertex	/* back pointer to vertex */
#define	f_bus		f_c.c_bus	/* which bus the card is in */
#define	f_slot		f_c.c_slot	/* which slot the card is in */
#define	f_func		f_c.c_func	/* which func (on multi-func cards) */
#define	f_vendor	f_c.c_vendor	/* PCI card "vendor" code */
#define	f_device	f_c.c_device	/* PCI card "device" code */
#define	f_master	f_c.c_master	/* PCI bus provider */
#define	f_mfast		f_c.c_mfast	/* cached fastinfo from c_master */
#define	f_pops		f_c.c_pops	/* cached provider from c_master */
#define	f_efunc		f_c.c_efunc	/* error handling function */
#define	f_einfo		f_c.c_einfo	/* first parameter for efunc */
#define	f_window	f_c.c_window	/* state of BASE regs */
#define	f_rwindow	f_c.c_rwindow	/* expansion ROM BASE regs */
#define	f_rbase		f_c.c_rbase	/* expansion ROM base */
#define	f_rsize		f_c.c_rsize	/* expansion ROM size */
#define	f_piospace	f_c.c_piospace	/* additional I/O spaces allocated */

    /* pcibr-specific connection state */
    int			    f_ibit[4];	/* Bridge bit for each INTx */
    pcibr_piomap_t	    f_piomap;
    int                     f_att_det_error;
    pciio_slot_t	    f_dev;	/* which device the card represents */
    cap_pcix_type0_t	   *f_pcix_cap;	/* pointer to the pcix capability */
};

/* =====================================================================
 *          Shared Interrupt Information
 */

struct pcibr_intr_list_s {
    pcibr_intr_list_t       il_next;
    pcibr_intr_t            il_intr;
    pcibr_soft_t	    il_soft;
    pciio_slot_t	    il_slot;
};

/* =====================================================================
 *          Interrupt Wrapper Data
 */
struct pcibr_intr_wrap_s {
    pcibr_soft_t            iw_soft;	/* which bridge */
    volatile bridgereg_t   *iw_stat;	/* ptr to b_int_status */
    bridgereg_t             iw_ibit;	/* bit in b_int_status */
    pcibr_intr_list_t       iw_list;	/* ghostbusters! */
    int			    iw_hdlrcnt;	/* running handler count */
    int			    iw_shared;  /* if Bridge bit is shared */
    int			    iw_connected; /* if already connected */
};

#define	PCIBR_ISR_ERR_START		8
#define PCIBR_ISR_MAX_ERRS_BRIDGE 	32
#define PCIBR_ISR_MAX_ERRS_PIC		45
#define PCIBR_ISR_MAX_ERRS	PCIBR_ISR_MAX_ERRS_PIC

/*
 * PCI Base Address Register window allocation constants.
 * To reduce the size of the internal resource mapping structures, do
 * not use the entire PCI bus I/O address space
 */ 
#define PCIBR_BUS_IO_BASE      0x200000
#define PCIBR_BUS_IO_MAX       0x0FFFFFFF
#define PCIBR_BUS_IO_PAGE      0x100000

#define PCIBR_BUS_SWIN_BASE    PAGE_SIZE
#define PCIBR_BUS_SWIN_MAX     0x000FFFFF
#define PCIBR_BUS_SWIN_PAGE    PAGE_SIZE

#define PCIBR_BUS_MEM_BASE     0x200000
#define PCIBR_BUS_MEM_MAX      0x3FFFFFFF
#define PCIBR_BUS_MEM_PAGE     0x100000

/* defines for pcibr_soft_s->bs_bridge_type */
#define PCIBR_BRIDGETYPE_PIC		2
#define IS_PIC_BUSNUM_SOFT(ps, bus)	((ps)->bs_busnum == (bus))

/*
 * Runtime checks for workarounds.
 */
#define PCIBR_WAR_ENABLED(pv, pcibr_soft) \
	((1 << XWIDGET_PART_REV_NUM_REV(pcibr_soft->bs_rev_num)) & pv)

/* defines for pcibr_soft_s->bs_bridge_mode */
#define PCIBR_BRIDGEMODE_PCI_33		0x0
#define PCIBR_BRIDGEMODE_PCI_66		0x2
#define PCIBR_BRIDGEMODE_PCIX_66	0x3
#define PCIBR_BRIDGEMODE_PCIX_100	0x5
#define PCIBR_BRIDGEMODE_PCIX_133	0x7
#define BUSSPEED_MASK			0x6
#define BUSTYPE_MASK			0x1

#define IS_PCI(ps)	(!IS_PCIX(ps))
#define IS_PCIX(ps)	((ps)->bs_bridge_mode & BUSTYPE_MASK)

#define IS_33MHZ(ps)	((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_33)
#define IS_66MHZ(ps)	(((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_66) || \
			 ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_66))
#define IS_100MHZ(ps)	((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_100)
#define IS_133MHZ(ps)	((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_133)


/* Number of PCI slots.   NOTE: this works as long as the first slot
 * is zero.  Otherwise use ((ps->bs_max_slot+1) - ps->bs_min_slot)
 */
#define PCIBR_NUM_SLOTS(ps) (ps->bs_max_slot+1)

/* =====================================================================
 *            Bridge Device State structure
 *
 *      one instance of this structure is kept for each
 *      Bridge ASIC in the system.
 */

struct pcibr_soft_s {
    vertex_hdl_t          bs_conn;		/* xtalk connection point */
    vertex_hdl_t          bs_vhdl;		/* vertex owned by pcibr */
    uint64_t                bs_int_enable;	/* Mask of enabled intrs */
    void               *bs_base;		/* PIO pointer to Bridge chip */
    char                   *bs_name;		/* hw graph name */
    char		    bs_asic_name[16];	/* ASIC name */
    xwidgetnum_t            bs_xid;		/* Bridge's xtalk ID number */
    vertex_hdl_t          bs_master;		/* xtalk master vertex */
    xwidgetnum_t            bs_mxid;		/* master's xtalk ID number */
    pciio_slot_t            bs_first_slot;      /* first existing slot */
    pciio_slot_t            bs_last_slot;       /* last existing slot */
    pciio_slot_t            bs_last_reset;      /* last slot to reset */
    uint32_t		    bs_unused_slot;	/* unavailable slots bitmask */
    pciio_slot_t	    bs_min_slot;	/* lowest possible slot */
    pciio_slot_t	    bs_max_slot;	/* highest possible slot */
    pcibr_soft_t	    bs_peers_soft;	/* PICs other bus's soft */
    int			    bs_busnum;		/* PIC has two pci busses */

    iopaddr_t               bs_dir_xbase;	/* xtalk address for 32-bit PCI direct map */
    xwidgetnum_t	    bs_dir_xport;	/* xtalk port for 32-bit PCI direct map */

    struct resource	    bs_int_ate_resource;/* root resource for internal ATEs */
    struct resource	    bs_ext_ate_resource;/* root resource for external ATEs */
    void	 	    *bs_allocated_ate_res;/* resource struct allocated */
    short		    bs_int_ate_size;	/* number of internal ates */
    short		    bs_bridge_type;	/* see defines above */
    short		    bs_bridge_mode;	/* see defines above */

    int                     bs_rev_num;	/* revision number of Bridge */

    /* bs_dma_flags are the forced dma flags used on all DMAs. Used for
     * working around ASIC rev issues and protocol specific requirements
     */
    unsigned int            bs_dma_flags;	/* forced DMA flags */

    nasid_t		    bs_nasid;		/* nasid this bus is on */
    moduleid_t		    bs_moduleid;	/* io brick moduleid */
    short		    bs_bricktype;	/* io brick type */

    /*
     * Lock used primarily to get mutual exclusion while managing any
     * bridge resources..
     */
    spinlock_t              bs_lock;
    
    vertex_hdl_t	    bs_noslot_conn;	/* NO-SLOT connection point */
    pcibr_info_t	    bs_noslot_info;

#ifdef CONFIG_HOTPLUG_PCI_SGI
    /* Linux PCI bus structure pointer */
    struct pci_bus         *bs_pci_bus;
#endif

    struct pcibr_soft_slot_s {
	/* information we keep about each CFG slot */

	/* some devices (ioc3 in non-slotted
	 * configurations, sometimes) make use
	 * of more than one REQ/GNT/INT* signal
	 * sets. The slot corresponding to the
	 * IDSEL that the device responds to is
	 * called the host slot; the slot
	 * numbers that the device is stealing
	 * REQ/GNT/INT bits from are known as
	 * the guest slots.
	 */
	int                     has_host;
	pciio_slot_t            host_slot;
	vertex_hdl_t		slot_conn;

#ifdef CONFIG_HOTPLUG_PCI_SGI
        /* PCI Hot-Plug status word */
        int 			slot_status;

	/* PCI Hot-Plug core structure pointer */
	struct hotplug_slot    *bss_hotplug_slot;
#endif	/* CONFIG_HOTPLUG_PCI_SGI */

	/* Potentially several connection points
	 * for this slot. bss_ninfo is how many,
	 * and bss_infos is a pointer to
	 * an array pcibr_info_t values (which are
	 * pointers to pcibr_info structs, stored
	 * as device_info in connection ponts).
	 */
	int			bss_ninfo;
	pcibr_info_h	        bss_infos;

	/* Temporary Compatibility Macros, for
	 * stuff that has moved out of bs_slot
	 * and into the info structure. These
	 * will go away when their users have
	 * converted over to multifunction-
	 * friendly use of bss_{ninfo,infos}.
	 */
#define	bss_vendor_id	bss_infos[0]->f_vendor
#define	bss_device_id	bss_infos[0]->f_device
#define	bss_window	bss_infos[0]->f_window
#define	bssw_space	w_space
#define	bssw_base	w_base
#define	bssw_size	w_size

	/* Where is DevIO(x) pointing? */
	/* bssd_space is NONE if it is not assigned. */
	struct {
	    pciio_space_t           bssd_space;
	    iopaddr_t               bssd_base;
            int                     bssd_ref_cnt;
	} bss_devio;

	/* Shadow value for Device(x) register,
	 * so we don't have to go to the chip.