pcibr_private.h
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/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. */#ifndef _ASM_IA64_SN_PCI_PCIBR_PRIVATE_H#define _ASM_IA64_SN_PCI_PCIBR_PRIVATE_H/* * pcibr_private.h -- private definitions for pcibr * only the pcibr driver (and its closest friends) * should ever peek into this file. */#include <linux/pci.h>#include <asm/sn/pci/pcibr.h>#include <asm/sn/pci/pciio_private.h>/* * convenience typedefs */typedef uint64_t pcibr_DMattr_t;typedef uint32_t pcibr_ATEattr_t;typedef struct pcibr_info_s *pcibr_info_t, **pcibr_info_h;typedef struct pcibr_soft_s *pcibr_soft_t;typedef struct pcibr_soft_slot_s *pcibr_soft_slot_t;typedef struct pcibr_hints_s *pcibr_hints_t;typedef struct pcibr_intr_list_s *pcibr_intr_list_t;typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t;typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t;typedef volatile unsigned int *cfg_p;typedef volatile bridgereg_t *reg_p;/* * extern functions */cfg_p pcibr_slot_config_addr(pcibr_soft_t, pciio_slot_t, int);cfg_p pcibr_func_config_addr(pcibr_soft_t, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int);void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...);void pcibr_func_config_set(pcibr_soft_t, pciio_slot_t, pciio_function_t, int, unsigned);/* * pcireg_ externs */extern uint64_t pcireg_id_get(pcibr_soft_t);extern uint64_t pcireg_bridge_id_get(void *);extern uint64_t pcireg_bus_err_get(pcibr_soft_t);extern uint64_t pcireg_control_get(pcibr_soft_t);extern uint64_t pcireg_bridge_control_get(void *);extern void pcireg_control_set(pcibr_soft_t, uint64_t);extern void pcireg_control_bit_clr(pcibr_soft_t, uint64_t);extern void pcireg_control_bit_set(pcibr_soft_t, uint64_t);extern void pcireg_req_timeout_set(pcibr_soft_t, uint64_t);extern void pcireg_intr_dst_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_intr_dst_target_id_get(pcibr_soft_t);extern void pcireg_intr_dst_target_id_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_intr_dst_addr_get(pcibr_soft_t);extern void pcireg_intr_dst_addr_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_cmdword_err_get(pcibr_soft_t);extern uint64_t pcireg_llp_cfg_get(pcibr_soft_t);extern void pcireg_llp_cfg_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_tflush_get(pcibr_soft_t);extern uint64_t pcireg_linkside_err_get(pcibr_soft_t);extern uint64_t pcireg_resp_err_get(pcibr_soft_t);extern uint64_t pcireg_resp_err_addr_get(pcibr_soft_t);extern uint64_t pcireg_resp_err_buf_get(pcibr_soft_t);extern uint64_t pcireg_resp_err_dev_get(pcibr_soft_t);extern uint64_t pcireg_linkside_err_addr_get(pcibr_soft_t);extern uint64_t pcireg_dirmap_get(pcibr_soft_t);extern void pcireg_dirmap_set(pcibr_soft_t, uint64_t);extern void pcireg_dirmap_wid_set(pcibr_soft_t, uint64_t);extern void pcireg_dirmap_diroff_set(pcibr_soft_t, uint64_t);extern void pcireg_dirmap_add512_set(pcibr_soft_t);extern void pcireg_dirmap_add512_clr(pcibr_soft_t);extern uint64_t pcireg_map_fault_get(pcibr_soft_t);extern uint64_t pcireg_arbitration_get(pcibr_soft_t);extern void pcireg_arbitration_set(pcibr_soft_t, uint64_t);extern void pcireg_arbitration_bit_clr(pcibr_soft_t, uint64_t);extern void pcireg_arbitration_bit_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_parity_err_get(pcibr_soft_t);extern uint64_t pcireg_type1_cntr_get(pcibr_soft_t);extern void pcireg_type1_cntr_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_timeout_get(pcibr_soft_t);extern void pcireg_timeout_set(pcibr_soft_t, uint64_t);extern void pcireg_timeout_bit_clr(pcibr_soft_t, uint64_t);extern void pcireg_timeout_bit_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_pci_bus_addr_get(pcibr_soft_t);extern uint64_t pcireg_pci_bus_addr_addr_get(pcibr_soft_t);extern uint64_t pcireg_intr_status_get(pcibr_soft_t);extern uint64_t pcireg_intr_enable_get(pcibr_soft_t);extern void pcireg_intr_enable_set(pcibr_soft_t, uint64_t);extern void pcireg_intr_enable_bit_clr(pcibr_soft_t, uint64_t);extern void pcireg_intr_enable_bit_set(pcibr_soft_t, uint64_t);extern void pcireg_intr_reset_set(pcibr_soft_t, uint64_t);extern void pcireg_intr_reset_bit_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_intr_mode_get(pcibr_soft_t);extern void pcireg_intr_mode_set(pcibr_soft_t, uint64_t);extern void pcireg_intr_mode_bit_clr(pcibr_soft_t, uint64_t);extern uint64_t pcireg_intr_device_get(pcibr_soft_t);extern void pcireg_intr_device_set(pcibr_soft_t, uint64_t);extern void pcireg_intr_device_bit_set(pcibr_soft_t, uint64_t);extern void pcireg_bridge_intr_device_bit_set(void *, uint64_t);extern void pcireg_intr_device_bit_clr(pcibr_soft_t, uint64_t);extern uint64_t pcireg_intr_host_err_get(pcibr_soft_t);extern void pcireg_intr_host_err_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_intr_addr_get(pcibr_soft_t, int);extern void pcireg_intr_addr_set(pcibr_soft_t, int, uint64_t);extern void pcireg_bridge_intr_addr_set(void *, int, uint64_t);extern void * pcireg_intr_addr_addr(pcibr_soft_t, int);extern void pcireg_intr_addr_vect_set(pcibr_soft_t, int, uint64_t);extern void pcireg_bridge_intr_addr_vect_set(void *, int, uint64_t);extern uint64_t pcireg_intr_addr_addr_get(pcibr_soft_t, int);extern void pcireg_intr_addr_addr_set(pcibr_soft_t, int, uint64_t);extern void pcireg_bridge_intr_addr_addr_set(void *, int, uint64_t);extern uint64_t pcireg_intr_view_get(pcibr_soft_t);extern uint64_t pcireg_intr_multiple_get(pcibr_soft_t);extern void pcireg_force_always_set(pcibr_soft_t, int);extern void * pcireg_bridge_force_always_addr_get(void *, int);extern void * pcireg_force_always_addr_get(pcibr_soft_t, int);extern void pcireg_force_intr_set(pcibr_soft_t, int);extern uint64_t pcireg_device_get(pcibr_soft_t, int);extern void pcireg_device_set(pcibr_soft_t, int, uint64_t);extern void pcireg_device_bit_set(pcibr_soft_t, int, uint64_t);extern void pcireg_device_bit_clr(pcibr_soft_t, int, uint64_t);extern uint64_t pcireg_rrb_get(pcibr_soft_t, int);extern void pcireg_rrb_set(pcibr_soft_t, int, uint64_t);extern void pcireg_rrb_bit_set(pcibr_soft_t, int, uint64_t);extern void pcireg_rrb_bit_clr(pcibr_soft_t, int, uint64_t);extern uint64_t pcireg_rrb_status_get(pcibr_soft_t);extern void pcireg_rrb_clear_set(pcibr_soft_t, uint64_t);extern uint64_t pcireg_wrb_flush_get(pcibr_soft_t, int);extern uint64_t pcireg_pcix_bus_err_addr_get(pcibr_soft_t);extern uint64_t pcireg_pcix_bus_err_attr_get(pcibr_soft_t);extern uint64_t pcireg_pcix_bus_err_data_get(pcibr_soft_t);extern uint64_t pcireg_pcix_req_err_attr_get(pcibr_soft_t);extern uint64_t pcireg_pcix_req_err_addr_get(pcibr_soft_t);extern uint64_t pcireg_pcix_pio_split_addr_get(pcibr_soft_t);extern uint64_t pcireg_pcix_pio_split_attr_get(pcibr_soft_t);extern cfg_p pcireg_type1_cfg_addr(pcibr_soft_t, pciio_function_t, int);extern cfg_p pcireg_type0_cfg_addr(pcibr_soft_t, pciio_slot_t, pciio_function_t, int);extern bridge_ate_t pcireg_int_ate_get(pcibr_soft_t, int);extern void pcireg_int_ate_set(pcibr_soft_t, int, bridge_ate_t);extern bridge_ate_p pcireg_int_ate_addr(pcibr_soft_t, int);extern uint64_t pcireg_speed_get(pcibr_soft_t);extern uint64_t pcireg_mode_get(pcibr_soft_t);/* * PCIBR_DEBUG() macro and debug bitmask defines *//* low freqency debug events (ie. initialization, resource allocation,...) */#define PCIBR_DEBUG_INIT 0x00000001 /* bridge init */#define PCIBR_DEBUG_HINTS 0x00000002 /* bridge hints */#define PCIBR_DEBUG_ATTACH 0x00000004 /* bridge attach */#define PCIBR_DEBUG_DETACH 0x00000008 /* bridge detach */#define PCIBR_DEBUG_ATE 0x00000010 /* bridge ATE allocation */#define PCIBR_DEBUG_RRB 0x00000020 /* bridge RRB allocation */#define PCIBR_DEBUG_RBAR 0x00000040 /* bridge RBAR allocation */#define PCIBR_DEBUG_PROBE 0x00000080 /* bridge device probing */#define PCIBR_DEBUG_INTR_ERROR 0x00000100 /* bridge error interrupt */#define PCIBR_DEBUG_ERROR_HDLR 0x00000200 /* bridge error handler */#define PCIBR_DEBUG_CONFIG 0x00000400 /* device's config space */#define PCIBR_DEBUG_BAR 0x00000800 /* device's BAR allocations */#define PCIBR_DEBUG_INTR_ALLOC 0x00001000 /* device's intr allocation */#define PCIBR_DEBUG_DEV_ATTACH 0x00002000 /* device's attach */#define PCIBR_DEBUG_DEV_DETACH 0x00004000 /* device's detach */#define PCIBR_DEBUG_HOTPLUG 0x00008000/* high freqency debug events (ie. map allocation, direct translation,...) */#define PCIBR_DEBUG_DEVREG 0x04000000 /* bridges device reg sets */#define PCIBR_DEBUG_PIOMAP 0x08000000 /* pcibr_piomap */#define PCIBR_DEBUG_PIODIR 0x10000000 /* pcibr_piotrans */#define PCIBR_DEBUG_DMAMAP 0x20000000 /* pcibr_dmamap */#define PCIBR_DEBUG_DMADIR 0x40000000 /* pcibr_dmatrans */#define PCIBR_DEBUG_INTR 0x80000000 /* interrupts */extern char *pcibr_debug_module;extern int pcibr_debug_widget;extern int pcibr_debug_slot;extern uint32_t pcibr_debug_mask;/* For low frequency events (ie. initialization, resource allocation,...) */#define PCIBR_DEBUG_ALWAYS(args) pcibr_debug args ;/* XXX: habeck: maybe make PCIBR_DEBUG() always available? Even in non- * debug kernels? If tracing isn't enabled (i.e pcibr_debug_mask isn't * set, then the overhead for this macro is just an extra 'if' check. *//* For high frequency events (ie. map allocation, direct translation,...) */#if DEBUG#define PCIBR_DEBUG(args) PCIBR_DEBUG_ALWAYS(args)#else /* DEBUG */#define PCIBR_DEBUG(args)#endif /* DEBUG *//* * Bridge sets up PIO using this information. */struct pcibr_piomap_s { struct pciio_piomap_s bp_pp; /* generic stuff */#define bp_flags bp_pp.pp_flags /* PCIBR_PIOMAP flags */#define bp_dev bp_pp.pp_dev /* associated pci card */#define bp_slot bp_pp.pp_slot /* which slot the card is in */#define bp_space bp_pp.pp_space /* which address space */#define bp_pciaddr bp_pp.pp_pciaddr /* starting offset of mapping */#define bp_mapsz bp_pp.pp_mapsz /* size of this mapping */#define bp_kvaddr bp_pp.pp_kvaddr /* kernel virtual address to use */ iopaddr_t bp_xtalk_addr; /* corresponding xtalk address */ xtalk_piomap_t bp_xtalk_pio; /* corresponding xtalk resource */ pcibr_piomap_t bp_next; /* Next piomap on the list */ pcibr_soft_t bp_soft; /* backpointer to bridge soft data */ atomic_t bp_toc; /* PCI timeout counter */};/* * Bridge sets up DMA using this information. */struct pcibr_dmamap_s { struct pciio_dmamap_s bd_pd;#define bd_flags bd_pd.pd_flags /* PCIBR_DMAMAP flags */#define bd_dev bd_pd.pd_dev /* associated pci card */#define bd_slot bd_pd.pd_slot /* which slot the card is in */ struct pcibr_soft_s *bd_soft; /* pcibr soft state backptr */ xtalk_dmamap_t bd_xtalk; /* associated xtalk resources */ size_t bd_max_size; /* maximum size of mapping */ xwidgetnum_t bd_xio_port; /* target XIO port */ iopaddr_t bd_xio_addr; /* target XIO address */ iopaddr_t bd_pci_addr; /* via PCI address */ int bd_ate_index; /* Address Translation Entry Index */ int bd_ate_count; /* number of ATE's allocated */ bridge_ate_p bd_ate_ptr; /* where to write first ATE */ bridge_ate_t bd_ate_proto; /* prototype ATE (for xioaddr=0) */ bridge_ate_t bd_ate_prime; /* value of 1st ATE written */ dma_addr_t bd_dma_addr; /* Linux dma handle */ struct resource resource;};#define IBUFSIZE 5 /* size of circular buffer (holds 4) *//* * Circular buffer used for interrupt processing */struct pcibr_intr_cbuf_s { spinlock_t ib_lock; /* cbuf 'put' lock */ int ib_in; /* index of next free entry */ int ib_out; /* index of next full entry */ pcibr_intr_wrap_t ib_cbuf[IBUFSIZE]; /* circular buffer of wrap */};/* * Bridge sets up interrupts using this information. */struct pcibr_intr_s { struct pciio_intr_s bi_pi;#define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */#define bi_dev bi_pi.pi_dev /* associated pci card */#define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */#define bi_func bi_pi.pi_func /* handler function (when connected) */⌨️ 快捷键说明
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