dmascc.c

优龙2410linux2.6.8内核源代码

	}

	info->dev[1] = alloc_netdev(0, "", dev_setup);
	if (!info->dev[1]) {
		printk(KERN_ERR "dmascc: "
			"could not allocate memory for %s at %#3x\n",
			hw[type].name, card_base);
		goto out2;
	}
	spin_lock_init(&info->register_lock);

	priv = &info->priv[0];
	priv->type = type;
	priv->card_base = card_base;
	priv->scc_cmd = scc_base + SCCA_CMD;
	priv->scc_data = scc_base + SCCA_DATA;
	priv->register_lock = &info->register_lock;

	/* Reset SCC */
	write_scc(priv, R9, FHWRES | MIE | NV);

	/* Determine type of chip by enabling SDLC/HDLC enhancements */
	write_scc(priv, R15, SHDLCE);
	if (!read_scc(priv, R15)) {
		/* WR7' not present. This is an ordinary Z8530 SCC. */
		chip = Z8530;
	} else {
		/* Put one character in TX FIFO */
		write_scc_data(priv, 0, 0);
		if (read_scc(priv, R0) & Tx_BUF_EMP) {
			/* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
			chip = Z85230;
		} else {
			/* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
			chip = Z85C30;
		}
	}
	write_scc(priv, R15, 0);

	/* Start IRQ auto-detection */
	irqs = probe_irq_on();

	/* Enable interrupts */
	if (type == TYPE_TWIN) {
		outb(0, card_base + TWIN_DMA_CFG);
		inb(card_base + TWIN_CLR_TMR1);
		inb(card_base + TWIN_CLR_TMR2);
		info->twin_serial_cfg = TWIN_EI;
		outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
	} else {
		write_scc(priv, R15, CTSIE);
		write_scc(priv, R0, RES_EXT_INT);
		write_scc(priv, R1, EXT_INT_ENAB);
	}

	/* Start timer */
	outb(1, tmr_base + TMR_CNT1);
	outb(0, tmr_base + TMR_CNT1);

	/* Wait and detect IRQ */
	time = jiffies; while (jiffies - time < 2 + HZ / TMR_0_HZ);
	irq = probe_irq_off(irqs);

	/* Clear pending interrupt, disable interrupts */
	if (type == TYPE_TWIN) {
		inb(card_base + TWIN_CLR_TMR1);
	} else {
		write_scc(priv, R1, 0);
		write_scc(priv, R15, 0);
		write_scc(priv, R0, RES_EXT_INT);
	}

	if (irq <= 0) {
		printk(KERN_ERR "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
			hw[type].name, card_base, irq);
		goto out3;
	}

	/* Set up data structures */
	for (i = 0; i < 2; i++) {
		dev = info->dev[i];
		priv = &info->priv[i];
		priv->type = type;
		priv->chip = chip;
		priv->dev = dev;
		priv->info = info;
		priv->channel = i;
		spin_lock_init(&priv->ring_lock);
		priv->register_lock = &info->register_lock;
		priv->card_base = card_base;
		priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
		priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
		priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
		priv->tmr_ctrl = tmr_base + TMR_CTRL;
		priv->tmr_mode = i ? 0xb0 : 0x70;
		priv->param.pclk_hz = hw[type].pclk_hz;
		priv->param.brg_tc = -1;
		priv->param.clocks = TCTRxCP | RCRTxCP;
		priv->param.persist = 256;
		priv->param.dma = -1;
		INIT_WORK(&priv->rx_work, rx_bh, priv);
		dev->priv = priv;
		sprintf(dev->name, "dmascc%i", 2*n+i);
		SET_MODULE_OWNER(dev);
		dev->base_addr = card_base;
		dev->irq = irq;
		dev->open = scc_open;
		dev->stop = scc_close;
		dev->do_ioctl = scc_ioctl;
		dev->hard_start_xmit = scc_send_packet;
		dev->get_stats = scc_get_stats;
		dev->hard_header = ax25_encapsulate;
		dev->rebuild_header = ax25_rebuild_header;
		dev->set_mac_address = scc_set_mac_address;
	}
	if (register_netdev(info->dev[0])) {
		printk(KERN_ERR "dmascc: could not register %s\n",
				info->dev[0]->name);
		goto out3;
	}
	if (register_netdev(info->dev[1])) {
		printk(KERN_ERR "dmascc: could not register %s\n",
				info->dev[1]->name);
		goto out4;
	}


	info->next = first;
	first = info;
	printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n", hw[type].name,
	chipnames[chip], card_base, irq);
	return 0;

out4:
	unregister_netdev(info->dev[0]);
out3:
	if (info->priv[0].type == TYPE_TWIN)
		outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
	write_scc(&info->priv[0], R9, FHWRES);
	free_netdev(info->dev[1]);
out2:
	free_netdev(info->dev[0]);
out1:
	kfree(info);
out:
	return -1;
}


/* Driver functions */

static void write_scc(struct scc_priv *priv, int reg, int val) {
  unsigned long flags;
  switch (priv->type) {
  case TYPE_S5:
    if (reg) outb(reg, priv->scc_cmd);
    outb(val, priv->scc_cmd);
    return;
  case TYPE_TWIN:
    if (reg) outb_p(reg, priv->scc_cmd);
    outb_p(val, priv->scc_cmd);
    return;
  default:
    spin_lock_irqsave(priv->register_lock, flags);
    outb_p(0, priv->card_base + PI_DREQ_MASK);
    if (reg) outb_p(reg, priv->scc_cmd);
    outb_p(val, priv->scc_cmd);
    outb(1, priv->card_base + PI_DREQ_MASK);
    spin_unlock_irqrestore(priv->register_lock, flags);
    return;
  }
}


static void write_scc_data(struct scc_priv *priv, int val, int fast) {
  unsigned long flags;
  switch (priv->type) {
  case TYPE_S5:
    outb(val, priv->scc_data);
    return;
  case TYPE_TWIN:
    outb_p(val, priv->scc_data);
    return;
  default:
    if (fast) outb_p(val, priv->scc_data);
    else {
      spin_lock_irqsave(priv->register_lock, flags);
      outb_p(0, priv->card_base + PI_DREQ_MASK);
      outb_p(val, priv->scc_data);
      outb(1, priv->card_base + PI_DREQ_MASK);
      spin_unlock_irqrestore(priv->register_lock, flags);
    }
    return;
  }
}


static int read_scc(struct scc_priv *priv, int reg) {
  int rc;
  unsigned long flags;
  switch (priv->type) {
  case TYPE_S5:
    if (reg) outb(reg, priv->scc_cmd);
    return inb(priv->scc_cmd);
  case TYPE_TWIN:
    if (reg) outb_p(reg, priv->scc_cmd);
    return inb_p(priv->scc_cmd);
  default:
    spin_lock_irqsave(priv->register_lock, flags);
    outb_p(0, priv->card_base + PI_DREQ_MASK);
    if (reg) outb_p(reg, priv->scc_cmd);
    rc = inb_p(priv->scc_cmd);
    outb(1, priv->card_base + PI_DREQ_MASK);
    spin_unlock_irqrestore(priv->register_lock, flags);
    return rc;
  }
}


static int read_scc_data(struct scc_priv *priv) {
  int rc;
  unsigned long flags;
  switch (priv->type) {
  case TYPE_S5:
    return inb(priv->scc_data);
  case TYPE_TWIN:
    return inb_p(priv->scc_data);
  default:
    spin_lock_irqsave(priv->register_lock, flags);
    outb_p(0, priv->card_base + PI_DREQ_MASK);
    rc = inb_p(priv->scc_data);
    outb(1, priv->card_base + PI_DREQ_MASK);
    spin_unlock_irqrestore(priv->register_lock, flags);
    return rc;
  }
}


static int scc_open(struct net_device *dev) {
  struct scc_priv *priv = dev->priv;
  struct scc_info *info = priv->info;
  int card_base = priv->card_base;

  /* Request IRQ if not already used by other channel */
  if (!info->irq_used) {
    if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
      return -EAGAIN;
    }
  }
  info->irq_used++;

  /* Request DMA if required */
  if (priv->param.dma >= 0) {
    if (request_dma(priv->param.dma, "dmascc")) {
      if (--info->irq_used == 0) free_irq(dev->irq, info);
      return -EAGAIN;
    } else {
      unsigned long flags = claim_dma_lock();
      clear_dma_ff(priv->param.dma);
      release_dma_lock(flags);
    }
  }

  /* Initialize local variables */
  priv->rx_ptr = 0;
  priv->rx_over = 0;
  priv->rx_head = priv->rx_tail = priv->rx_count = 0;
  priv->state = IDLE;
  priv->tx_head = priv->tx_tail = priv->tx_count = 0;
  priv->tx_ptr = 0;

  /* Reset channel */
  write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
  /* X1 clock, SDLC mode */
  write_scc(priv, R4, SDLC | X1CLK);
  /* DMA */
  write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
  /* 8 bit RX char, RX disable */
  write_scc(priv, R3, Rx8);
  /* 8 bit TX char, TX disable */
  write_scc(priv, R5, Tx8);
  /* SDLC address field */
  write_scc(priv, R6, 0);
  /* SDLC flag */
  write_scc(priv, R7, FLAG);
  switch (priv->chip) {
  case Z85C30:
    /* Select WR7' */
    write_scc(priv, R15, SHDLCE);
    /* Auto EOM reset */
    write_scc(priv, R7, AUTOEOM);
    write_scc(priv, R15, 0);
    break;
  case Z85230:
    /* Select WR7' */
    write_scc(priv, R15, SHDLCE);
    /* The following bits are set (see 2.5.2.1):
       - Automatic EOM reset
       - Interrupt request if RX FIFO is half full
         This bit should be ignored in DMA mode (according to the
         documentation), but actually isn't. The receiver doesn't work if
         it is set. Thus, we have to clear it in DMA mode.
       - Interrupt/DMA request if TX FIFO is completely empty
         a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
            compatibility).
         b) If cleared, DMA requests may follow each other very quickly,
            filling up the TX FIFO.
            Advantage: TX works even in case of high bus latency.
            Disadvantage: Edge-triggered DMA request circuitry may miss
                          a request. No more data is delivered, resulting
                          in a TX FIFO underrun.
         Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
         The PackeTwin doesn't. I don't know about the PI, but let's
	 assume it behaves like the PI2.
    */
    if (priv->param.dma >= 0) {
      if (priv->type == TYPE_TWIN) write_scc(priv, R7, AUTOEOM | TXFIFOE);
      else write_scc(priv, R7, AUTOEOM);
    } else {
      write_scc(priv, R7, AUTOEOM | RXFIFOH);
    }
    write_scc(priv, R15, 0);
    break;
  }
  /* Preset CRC, NRZ(I) encoding */
  write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));

  /* Configure baud rate generator */
  if (priv->param.brg_tc >= 0) {
    /* Program BR generator */
    write_scc(priv, R12, priv->param.brg_tc & 0xFF);
    write_scc(priv, R13, (priv->param.brg_tc>>8) & 0xFF);
    /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
       PackeTwin, not connected on the PI2); set DPLL source to BRG */
    write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
    /* Enable DPLL */
    write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
  } else {
    /* Disable BR generator */
    write_scc(priv, R14, DTRREQ | BRSRC);
  }

  /* Configure clocks */
  if (priv->type == TYPE_TWIN) {
    /* Disable external TX clock receiver */
    outb((info->twin_serial_cfg &=
	    ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), 
	   card_base + TWIN_SERIAL_CFG);
  }
  write_scc(priv, R11, priv->param.clocks);
  if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
    /* Enable external TX clock receiver */
    outb((info->twin_serial_cfg |=
	    (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
	   card_base + TWIN_SERIAL_CFG);
  }

  /* Configure PackeTwin */
  if (priv->type == TYPE_TWIN) {
    /* Assert DTR, enable interrupts */
    outb((info->twin_serial_cfg |= TWIN_EI |
	    (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
	   card_base + TWIN_SERIAL_CFG);
  }

  /* Read current status */
  priv->rr0 = read_scc(priv, R0);
  /* Enable DCD interrupt */
  write_scc(priv, R15, DCDIE);

  netif_start_queue(dev);

  return 0;
}


static int scc_close(struct net_device *dev) {
  struct scc_priv *priv = dev->priv;
  struct scc_info *info = priv->info;
  int card_base = priv->card_base;

  netif_stop_queue(dev);

  if (priv->type == TYPE_TWIN) {
    /* Drop DTR */
    outb((info->twin_serial_cfg &=
	    (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
	   card_base + TWIN_SERIAL_CFG);
  }

  /* Reset channel, free DMA and IRQ */
  write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
  if (priv->param.dma >= 0) {
    if (priv->type == TYPE_TWIN) outb(0, card_base + TWIN_DMA_CFG);
    free_dma(priv->param.dma);
  }
  if (--info->irq_used == 0) free_irq(dev->irq, info);

  return 0;
}


static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) {
  struct scc_priv *priv = dev->priv;
  
  switch (cmd) {
  case SIOCGSCCPARAM:
    if (copy_to_user(ifr->ifr_data, &priv->param, sizeof(struct scc_param)))
      return -EFAULT;
    return 0;
  case SIOCSSCCPARAM:
    if (!capable(CAP_NET_ADMIN)) return -EPERM;
    if (netif_running(dev)) return -EAGAIN;
    if (copy_from_user(&priv->param, ifr->ifr_data, sizeof(struct scc_param)))
      return -EFAULT;
    return 0;
  default:
    return -EINVAL;
  }
}


static int scc_send_packet(struct sk_buff *skb, struct net_device *dev) {
  struct scc_priv *priv = dev->priv;
  unsigned long flags;
  int i;

  /* Temporarily stop the scheduler feeding us packets */
  netif_stop_queue(dev);

  /* Transfer data to DMA buffer */
  i = priv->tx_head;
  memcpy(priv->tx_buf[i], skb->data+1, skb->len-1);
  priv->tx_len[i] = skb->len-1;

  /* Clear interrupts while we touch our circular buffers */

  spin_lock_irqsave(&priv->ring_lock, flags);
  /* Move the ring buffer's head */
  priv->tx_head = (i + 1) % NUM_TX_BUF;
  priv->tx_count++;

  /* If we just filled up the last buffer, leave queue stopped.
     The higher layers must wait until we have a DMA buffer
     to accept the data. */
  if (priv->tx_count < NUM_TX_BUF) netif_wake_queue(dev);

  /* Set new TX state */
  if (priv->state == IDLE) {
    /* Assert RTS, start timer */
    priv->state = TX_HEAD;
    priv->tx_start = jiffies;
    write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
    write_scc(priv, R15, 0);
    start_timer(priv, priv->param.txdelay, 0);
  }

  /* Turn interrupts back on and free buffer */
  spin_unlock_irqrestore(&priv->ring_lock, flags);
  dev_kfree_skb(skb);

  return 0;
}


static struct net_device_stats *scc_get_stats(struct net_device *dev) {
  struct scc_priv *priv = dev->priv;

  return &priv->stats;