pc300-falc-lh.h

优龙2410linux2.6.8内核源代码

#define TSWM_TSA7       0x02
#define TSWM_TSA8       0x01

/* IDLE <Idle Channel Code Register>

   ------------------ E1 & T1 ----------------------- */

#define IDLE_IDL7       0x80
#define IDLE_IDL6       0x40
#define IDLE_IDL5       0x20
#define IDLE_IDL4       0x10
#define IDLE_IDL3       0x08
#define IDLE_IDL2       0x04
#define IDLE_IDL1       0x02
#define IDLE_IDL0       0x01


/* XSA4-8 <Transmit SA4-8 Register(Read/Write) >
   -------------------E1 ----------------------------- */

#define XSA4_XS47       0x80
#define XSA4_XS46       0x40
#define XSA4_XS45       0x20
#define XSA4_XS44       0x10
#define XSA4_XS43       0x08
#define XSA4_XS42       0x04
#define XSA4_XS41       0x02
#define XSA4_XS40       0x01

#define XSA5_XS57       0x80
#define XSA5_XS56       0x40
#define XSA5_XS55       0x20
#define XSA5_XS54       0x10
#define XSA5_XS53       0x08
#define XSA5_XS52       0x04
#define XSA5_XS51       0x02
#define XSA5_XS50       0x01

#define XSA6_XS67       0x80
#define XSA6_XS66       0x40
#define XSA6_XS65       0x20
#define XSA6_XS64       0x10
#define XSA6_XS63       0x08
#define XSA6_XS62       0x04
#define XSA6_XS61       0x02
#define XSA6_XS60       0x01

#define XSA7_XS77       0x80
#define XSA7_XS76       0x40
#define XSA7_XS75       0x20
#define XSA7_XS74       0x10
#define XSA7_XS73       0x08
#define XSA7_XS72       0x04
#define XSA7_XS71       0x02
#define XSA7_XS70       0x01

#define XSA8_XS87       0x80
#define XSA8_XS86       0x40
#define XSA8_XS85       0x20
#define XSA8_XS84       0x10
#define XSA8_XS83       0x08
#define XSA8_XS82       0x04
#define XSA8_XS81       0x02
#define XSA8_XS80       0x01


/* XDL1-3 (Transmit DL-Bit Register1-3 (read/write))
   ----------------------- T1 --------------------- */

#define XDL1_XDL17      0x80
#define XDL1_XDL16      0x40
#define XDL1_XDL15      0x20
#define XDL1_XDL14      0x10
#define XDL1_XDL13      0x08
#define XDL1_XDL12      0x04
#define XDL1_XDL11      0x02
#define XDL1_XDL10      0x01

#define XDL2_XDL27      0x80
#define XDL2_XDL26      0x40
#define XDL2_XDL25      0x20
#define XDL2_XDL24      0x10
#define XDL2_XDL23      0x08
#define XDL2_XDL22      0x04
#define XDL2_XDL21      0x02
#define XDL2_XDL20      0x01

#define XDL3_XDL37      0x80
#define XDL3_XDL36      0x40
#define XDL3_XDL35      0x20
#define XDL3_XDL34      0x10
#define XDL3_XDL33      0x08
#define XDL3_XDL32      0x04
#define XDL3_XDL31      0x02
#define XDL3_XDL30      0x01


/* ICB1-4 (Idle Channel Register 1-4)
   ------------------ E1 ---------------------------- */

#define E1_ICB1_IC0	0x80
#define E1_ICB1_IC1	0x40
#define E1_ICB1_IC2	0x20
#define E1_ICB1_IC3	0x10
#define E1_ICB1_IC4	0x08
#define E1_ICB1_IC5	0x04
#define E1_ICB1_IC6	0x02
#define E1_ICB1_IC7	0x01

#define E1_ICB2_IC8	0x80
#define E1_ICB2_IC9	0x40
#define E1_ICB2_IC10	0x20
#define E1_ICB2_IC11	0x10
#define E1_ICB2_IC12	0x08
#define E1_ICB2_IC13	0x04
#define E1_ICB2_IC14	0x02
#define E1_ICB2_IC15	0x01

#define E1_ICB3_IC16	0x80
#define E1_ICB3_IC17	0x40
#define E1_ICB3_IC18	0x20
#define E1_ICB3_IC19	0x10
#define E1_ICB3_IC20	0x08
#define E1_ICB3_IC21	0x04
#define E1_ICB3_IC22	0x02
#define E1_ICB3_IC23	0x01

#define E1_ICB4_IC24	0x80
#define E1_ICB4_IC25	0x40
#define E1_ICB4_IC26	0x20
#define E1_ICB4_IC27	0x10
#define E1_ICB4_IC28	0x08
#define E1_ICB4_IC29	0x04
#define E1_ICB4_IC30	0x02
#define E1_ICB4_IC31	0x01

/* ICB1-4 (Idle Channel Register 1-4)
   ------------------ T1 ---------------------------- */

#define T1_ICB1_IC1	0x80
#define T1_ICB1_IC2	0x40
#define T1_ICB1_IC3	0x20
#define T1_ICB1_IC4	0x10
#define T1_ICB1_IC5	0x08
#define T1_ICB1_IC6	0x04
#define T1_ICB1_IC7	0x02
#define T1_ICB1_IC8	0x01

#define T1_ICB2_IC9	0x80
#define T1_ICB2_IC10	0x40
#define T1_ICB2_IC11	0x20
#define T1_ICB2_IC12	0x10
#define T1_ICB2_IC13	0x08
#define T1_ICB2_IC14	0x04
#define T1_ICB2_IC15	0x02
#define T1_ICB2_IC16	0x01

#define T1_ICB3_IC17	0x80
#define T1_ICB3_IC18	0x40
#define T1_ICB3_IC19	0x20
#define T1_ICB3_IC20	0x10
#define T1_ICB3_IC21	0x08
#define T1_ICB3_IC22	0x04
#define T1_ICB3_IC23	0x02
#define T1_ICB3_IC24	0x01

/* FMR3 (Framer Mode Register 3)
   --------------------E1------------------------ */

#define FMR3_CMI        0x08
#define FMR3_SYNSA      0x04
#define FMR3_CFRZ       0x02
#define FMR3_EXTIW      0x01



/* CCB1-3 (Clear Channel Register)
   ------------------- T1 ----------------------- */

#define CCB1_CH1        0x80
#define CCB1_CH2        0x40
#define CCB1_CH3        0x20
#define CCB1_CH4        0x10
#define CCB1_CH5        0x08
#define CCB1_CH6        0x04
#define CCB1_CH7        0x02
#define CCB1_CH8        0x01

#define CCB2_CH9        0x80
#define CCB2_CH10       0x40
#define CCB2_CH11       0x20
#define CCB2_CH12       0x10
#define CCB2_CH13       0x08
#define CCB2_CH14       0x04
#define CCB2_CH15       0x02
#define CCB2_CH16       0x01

#define CCB3_CH17       0x80
#define CCB3_CH18       0x40
#define CCB3_CH19       0x20
#define CCB3_CH20       0x10
#define CCB3_CH21       0x08
#define CCB3_CH22       0x04
#define CCB3_CH23       0x02
#define CCB3_CH24       0x01


/* LIM0/1 (Line Interface Mode 0/1)
   ------------------- E1 & T1 --------------------------- */

#define LIM0_XFB        0x80
#define LIM0_XDOS       0x40
#define LIM0_SCL1       0x20
#define LIM0_SCL0       0x10
#define LIM0_EQON       0x08
#define LIM0_ELOS       0x04
#define LIM0_LL         0x02
#define LIM0_MAS        0x01

#define LIM1_EFSC       0x80
#define LIM1_RIL2       0x40
#define LIM1_RIL1       0x20
#define LIM1_RIL0       0x10
#define LIM1_DCOC       0x08
#define LIM1_JATT       0x04
#define LIM1_RL         0x02
#define LIM1_DRS        0x01


/* PCDR (Pulse Count Detection Register(Read/Write))
   ------------------ E1 & T1 ------------------------- */

#define PCDR_PCD7	0x80
#define PCDR_PCD6	0x40
#define PCDR_PCD5	0x20
#define PCDR_PCD4	0x10
#define PCDR_PCD3	0x08
#define PCDR_PCD2	0x04
#define PCDR_PCD1	0x02
#define PCDR_PCD0	0x01

#define PCRR_PCR7	0x80
#define PCRR_PCR6	0x40
#define PCRR_PCR5	0x20
#define PCRR_PCR4	0x10
#define PCRR_PCR3	0x08
#define PCRR_PCR2	0x04
#define PCRR_PCR1	0x02
#define PCRR_PCR0	0x01


/* LIM2 (Line Interface Mode 2)

   ------------------ E1 & T1 ---------------------------- */

#define LIM2_DJA2	0x20
#define LIM2_DJA1	0x10
#define LIM2_LOS2	0x02
#define LIM2_LOS1	0x01

/* LCR1 (Loop Code Register 1) */

#define LCR1_EPRM	0x80
#define	LCR1_XPRBS	0x40

/* SIC1 (System Interface Control 1) */
#define SIC1_SRSC	0x80
#define SIC1_RBS1	0x20
#define SIC1_RBS0	0x10
#define SIC1_SXSC	0x08
#define SIC1_XBS1	0x02
#define SIC1_XBS0	0x01

/* DEC (Disable Error Counter)
   ------------------ E1 & T1 ---------------------------- */

#define DEC_DCEC3       0x20
#define DEC_DBEC        0x10
#define DEC_DCEC1       0x08
#define DEC_DCEC        0x08
#define DEC_DEBC        0x04
#define DEC_DCVC        0x02
#define DEC_DFEC        0x01


/* FALC Register Bits (Receive Mode)
   ---------------------------------------------------------------------------- */


/* FRS0/1 (Framer Receive Status Register 0/1)
   ----------------- E1 & T1 ---------------------------------- */

#define FRS0_LOS        0x80
#define FRS0_AIS        0x40
#define FRS0_LFA        0x20
#define FRS0_RRA        0x10
#define FRS0_API        0x08
#define FRS0_NMF        0x04
#define FRS0_LMFA       0x02
#define FRS0_FSRF       0x01

#define FRS1_TS16RA     0x40
#define FRS1_TS16LOS    0x20
#define FRS1_TS16AIS    0x10
#define FRS1_TS16LFA    0x08
#define FRS1_EXZD       0x80
#define FRS1_LLBDD      0x10
#define FRS1_LLBAD      0x08
#define FRS1_XLS        0x02
#define FRS1_XLO        0x01
#define FRS1_PDEN	0x40

/* FRS2/3 (Framer Receive Status Register 2/3)
   ----------------- T1 ---------------------------------- */

#define FRS2_ESC2       0x80
#define FRS2_ESC1       0x40
#define FRS2_ESC0       0x20

#define FRS3_FEH5       0x20
#define FRS3_FEH4       0x10
#define FRS3_FEH3       0x08
#define FRS3_FEH2       0x04
#define FRS3_FEH1       0x02
#define FRS3_FEH0       0x01


/* RSW (Receive Service Word Pulseframe)
   ----------------- E1 ------------------------------ */

#define RSW_RSI         0x80
#define RSW_RRA         0x20
#define RSW_RYO         0x10
#define RSW_RY1         0x08
#define RSW_RY2         0x04
#define RSW_RY3         0x02
#define RSW_RY4         0x01


/* RSP (Receive Spare Bits / Additional Status)
   ---------------- E1 ------------------------------- */

#define RSP_SI1         0x80
#define RSP_SI2         0x40
#define RSP_LLBDD	0x10
#define RSP_LLBAD	0x08
#define RSP_RSIF        0x04
#define RSP_RS13        0x02
#define RSP_RS15        0x01


/* FECL (Framing Error Counter)
   ---------------- E1 & T1 -------------------------- */

#define FECL_FE7        0x80
#define FECL_FE6        0x40
#define FECL_FE5        0x20
#define FECL_FE4        0x10
#define FECL_FE3        0x08
#define FECL_FE2        0x04
#define FECL_FE1        0x02
#define FECL_FE0        0x01

#define FECH_FE15       0x80
#define FECH_FE14       0x40
#define FECH_FE13       0x20
#define FECH_FE12       0x10
#define FECH_FE11       0x08
#define FECH_FE10       0x04
#define FECH_FE9        0x02
#define FECH_FE8        0x01


/* CVCl (Code Violation Counter)
   ----------------- E1 ------------------------- */

#define CVCL_CV7        0x80
#define CVCL_CV6        0x40
#define CVCL_CV5        0x20
#define CVCL_CV4        0x10
#define CVCL_CV3        0x08
#define CVCL_CV2        0x04
#define CVCL_CV1        0x02
#define CVCL_CV0        0x01

#define CVCH_CV15       0x80
#define CVCH_CV14       0x40
#define CVCH_CV13       0x20
#define CVCH_CV12       0x10
#define CVCH_CV11       0x08
#define CVCH_CV10       0x04
#define CVCH_CV9        0x02
#define CVCH_CV8        0x01


/* CEC1-3L (CRC Error Counter)
   ------------------ E1 ----------------------------- */

#define CEC1L_CR7       0x80
#define CEC1L_CR6       0x40
#define CEC1L_CR5       0x20
#define CEC1L_CR4       0x10
#define CEC1L_CR3       0x08
#define CEC1L_CR2       0x04
#define CEC1L_CR1       0x02
#define CEC1L_CR0       0x01

#define CEC1H_CR15      0x80
#define CEC1H_CR14      0x40
#define CEC1H_CR13      0x20
#define CEC1H_CR12      0x10
#define CEC1H_CR11      0x08
#define CEC1H_CR10      0x04