pc300-falc-lh.h

优龙2410linux2.6.8内核源代码

/*
 * falc.h	Description of the Siemens FALC T1/E1 framer.
 *
 * Author:	Ivan Passos <[e-mail]>
 *
 * Copyright:	(c) 2000-2001 Cyclades Corp.
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 * $Log: falc-lh.h,v $
 * Revision 3.1  2001/06/15 12:41:10  regina
 * upping major version number
 *
 * Revision 1.1.1.1  2001/06/13 20:24:47  daniela
 * PC300 initial CVS version (3.4.0-pre1)
 *
 * Revision 1.1 2000/05/15 ivan
 * Included DJA bits for the LIM2 register.
 *
 * Revision 1.0 2000/02/22 ivan
 * Initial version.
 *
 */

#ifndef _FALC_LH_H
#define _FALC_LH_H

#define NUM_OF_T1_CHANNELS	24
#define NUM_OF_E1_CHANNELS	32

/*>>>>>>>>>>>>>>>>>  FALC Register Bits (Transmit Mode)  <<<<<<<<<<<<<<<<<<< */

/* CMDR (Command Register)
   ---------------- E1 & T1 ------------------------------ */
#define CMDR_RMC	0x80
#define CMDR_RRES	0x40
#define CMDR_XREP	0x20
#define CMDR_XRES	0x10
#define CMDR_XHF	0x08
#define CMDR_XTF	0x04
#define CMDR_XME	0x02
#define CMDR_SRES	0x01

/* MODE (Mode Register)
   ----------------- E1 & T1 ----------------------------- */
#define MODE_MDS2	0x80
#define MODE_MDS1	0x40
#define MODE_MDS0	0x20
#define MODE_BRAC	0x10
#define MODE_HRAC	0x08

/* IPC (Interrupt Port Configuration)
   ----------------- E1 & T1 ----------------------------- */
#define IPC_VIS		0x80
#define IPC_SCI		0x04
#define IPC_IC1		0x02
#define IPC_IC0		0x01

/* CCR1 (Common Configuration Register 1)
   ----------------- E1 & T1 ----------------------------- */
#define CCR1_SFLG       0x80
#define CCR1_XTS16RA    0x40
#define CCR1_BRM        0x40
#define CCR1_CASSYM     0x20
#define CCR1_EDLX       0x20
#define CCR1_EITS       0x10
#define CCR1_ITF        0x08
#define CCR1_RFT1       0x02
#define CCR1_RFT0       0x01

/* CCR3 (Common Configuration Register 3)
   ---------------- E1 & T1 ------------------------------ */

#define CCR3_PRE1       0x80
#define CCR3_PRE0       0x40
#define CCR3_EPT        0x20
#define CCR3_RADD       0x10
#define CCR3_RCRC       0x04
#define CCR3_XCRC       0x02


/* RTR1-4 (Receive Timeslot Register 1-4)
   ---------------- E1 & T1 ------------------------------ */

#define RTR1_TS0        0x80
#define RTR1_TS1        0x40
#define RTR1_TS2        0x20
#define RTR1_TS3        0x10
#define RTR1_TS4        0x08
#define RTR1_TS5        0x04
#define RTR1_TS6        0x02
#define RTR1_TS7        0x01

#define RTR2_TS8        0x80
#define RTR2_TS9        0x40
#define RTR2_TS10       0x20
#define RTR2_TS11       0x10
#define RTR2_TS12       0x08
#define RTR2_TS13       0x04
#define RTR2_TS14       0x02
#define RTR2_TS15       0x01

#define RTR3_TS16       0x80
#define RTR3_TS17       0x40
#define RTR3_TS18       0x20
#define RTR3_TS19       0x10
#define RTR3_TS20       0x08
#define RTR3_TS21       0x04
#define RTR3_TS22       0x02
#define RTR3_TS23       0x01

#define RTR4_TS24       0x80
#define RTR4_TS25       0x40
#define RTR4_TS26       0x20
#define RTR4_TS27       0x10
#define RTR4_TS28       0x08
#define RTR4_TS29       0x04
#define RTR4_TS30       0x02
#define RTR4_TS31       0x01


/* TTR1-4 (Transmit Timeslot Register 1-4)
   ---------------- E1 & T1 ------------------------------ */

#define TTR1_TS0        0x80
#define TTR1_TS1        0x40
#define TTR1_TS2        0x20
#define TTR1_TS3        0x10
#define TTR1_TS4        0x08
#define TTR1_TS5        0x04
#define TTR1_TS6        0x02
#define TTR1_TS7        0x01

#define TTR2_TS8        0x80
#define TTR2_TS9        0x40
#define TTR2_TS10       0x20
#define TTR2_TS11       0x10
#define TTR2_TS12       0x08
#define TTR2_TS13       0x04
#define TTR2_TS14       0x02
#define TTR2_TS15       0x01

#define TTR3_TS16       0x80
#define TTR3_TS17       0x40
#define TTR3_TS18       0x20
#define TTR3_TS19       0x10
#define TTR3_TS20       0x08
#define TTR3_TS21       0x04
#define TTR3_TS22       0x02
#define TTR3_TS23       0x01

#define TTR4_TS24       0x80
#define TTR4_TS25       0x40
#define TTR4_TS26       0x20
#define TTR4_TS27       0x10
#define TTR4_TS28       0x08
#define TTR4_TS29       0x04
#define TTR4_TS30       0x02
#define TTR4_TS31       0x01



/* IMR0-4 (Interrupt Mask Register 0-4)

   ----------------- E1 & T1 ----------------------------- */

#define IMR0_RME        0x80
#define IMR0_RFS        0x40
#define IMR0_T8MS       0x20
#define IMR0_ISF        0x20
#define IMR0_RMB        0x10
#define IMR0_CASC       0x08
#define IMR0_RSC        0x08
#define IMR0_CRC6       0x04
#define IMR0_CRC4       0x04
#define IMR0_PDEN	0x02
#define IMR0_RPF        0x01

#define IMR1_CASE       0x80
#define IMR1_RDO        0x40
#define IMR1_ALLS       0x20
#define IMR1_XDU        0x10
#define IMR1_XMB        0x08
#define IMR1_XLSC       0x02
#define IMR1_XPR        0x01
#define IMR1_LLBSC	0x80

#define IMR2_FAR        0x80
#define IMR2_LFA        0x40
#define IMR2_MFAR       0x20
#define IMR2_T400MS     0x10
#define IMR2_LMFA       0x10
#define IMR2_AIS        0x08
#define IMR2_LOS        0x04
#define IMR2_RAR        0x02
#define IMR2_RA         0x01

#define IMR3_ES         0x80
#define IMR3_SEC        0x40
#define IMR3_LMFA16     0x20
#define IMR3_AIS16      0x10
#define IMR3_RA16       0x08
#define IMR3_API        0x04
#define IMR3_XSLP       0x20
#define IMR3_XSLN       0x10
#define IMR3_LLBSC      0x08
#define IMR3_XRS        0x04
#define IMR3_SLN        0x02
#define IMR3_SLP        0x01

#define IMR4_LFA        0x80
#define IMR4_FER        0x40
#define IMR4_CER        0x20
#define IMR4_AIS        0x10
#define IMR4_LOS        0x08
#define IMR4_CVE        0x04
#define IMR4_SLIP       0x02
#define IMR4_EBE        0x01

/* FMR0-5 for E1 and T1  (Framer Mode Register ) */

#define FMR0_XC1        0x80
#define FMR0_XC0        0x40
#define FMR0_RC1        0x20
#define FMR0_RC0        0x10
#define FMR0_EXTD       0x08
#define FMR0_ALM        0x04
#define E1_FMR0_FRS     0x02
#define T1_FMR0_FRS     0x08
#define FMR0_SRAF       0x04
#define FMR0_EXLS       0x02
#define FMR0_SIM        0x01

#define FMR1_MFCS       0x80
#define FMR1_AFR        0x40
#define FMR1_ENSA       0x20
#define FMR1_CTM        0x80
#define FMR1_SIGM       0x40
#define FMR1_EDL        0x20
#define FMR1_PMOD       0x10
#define FMR1_XFS        0x08
#define FMR1_CRC        0x08
#define FMR1_ECM        0x04
#define FMR1_IMOD       0x02
#define FMR1_XAIS       0x01

#define FMR2_RFS1       0x80
#define FMR2_RFS0       0x40
#define FMR2_MCSP	0x40
#define FMR2_RTM        0x20
#define FMR2_SSP        0x20
#define FMR2_DAIS       0x10
#define FMR2_SAIS       0x08
#define FMR2_PLB        0x04
#define FMR2_AXRA       0x02
#define FMR2_ALMF       0x01
#define FMR2_EXZE       0x01

#define LOOP_RTM	0x40
#define LOOP_SFM	0x40
#define LOOP_ECLB	0x20
#define LOOP_CLA	0x1f

/*--------------------- E1 ----------------------------*/
#define FMR3_XLD	0x20
#define FMR3_XLU	0x10

/*--------------------- T1 ----------------------------*/
#define FMR4_AIS3       0x80
#define FMR4_TM         0x40
#define FMR4_XRA        0x20
#define FMR4_SSC1       0x10
#define FMR4_SSC0       0x08
#define FMR4_AUTO       0x04
#define FMR4_FM1        0x02
#define FMR4_FM0        0x01

#define FMR5_SRS        0x80
#define FMR5_EIBR       0x40
#define FMR5_XLD        0x20
#define FMR5_XLU        0x10


/* LOOP (Channel Loop Back)

   ------------------ E1 & T1 ---------------------------- */

#define LOOP_SFM        0x40
#define LOOP_ECLB       0x20
#define LOOP_CLA4       0x10
#define LOOP_CLA3       0x08
#define LOOP_CLA2       0x04
#define LOOP_CLA1       0x02
#define LOOP_CLA0       0x01



/* XSW (Transmit Service Word Pulseframe)

   ------------------- E1 --------------------------- */

#define XSW_XSIS        0x80
#define XSW_XTM         0x40
#define XSW_XRA         0x20
#define XSW_XY0         0x10
#define XSW_XY1         0x08
#define XSW_XY2         0x04
#define XSW_XY3         0x02
#define XSW_XY4         0x01


/* XSP (Transmit Spare Bits)

   ------------------- E1 --------------------------- */

#define XSP_XAP         0x80
#define XSP_CASEN       0x40
#define XSP_TT0         0x20
#define XSP_EBP         0x10
#define XSP_AXS         0x08
#define XSP_XSIF        0x04
#define XSP_XS13        0x02
#define XSP_XS15        0x01


/* XC0/1 (Transmit Control 0/1)
   ------------------ E1 & T1 ---------------------------- */

#define XC0_SA8E        0x80
#define XC0_SA7E        0x40
#define XC0_SA6E        0x20
#define XC0_SA5E        0x10
#define XC0_SA4E        0x08
#define XC0_BRM         0x80
#define XC0_MFBS        0x40
#define XC0_SFRZ        0x10
#define XC0_XCO2        0x04
#define XC0_XCO1        0x02
#define XC0_XCO0        0x01

#define XC1_XTO5        0x20
#define XC1_XTO4        0x10
#define XC1_XTO3        0x08
#define XC1_XTO2        0x04
#define XC1_XTO1        0x02
#define XC1_XTO0        0x01


/* RC0/1 (Receive Control 0/1)
   ------------------ E1 & T1 ---------------------------- */

#define RC0_SICS        0x40
#define RC0_CRCI        0x20
#define RC0_XCRCI       0x10
#define RC0_RDIS        0x08
#define RC0_RCO2        0x04
#define RC0_RCO1        0x02
#define RC0_RCO0        0x01

#define RC1_SWD         0x80
#define RC1_ASY4        0x40
#define RC1_RRAM        0x40
#define RC1_RTO5        0x20
#define RC1_RTO4        0x10
#define RC1_RTO3        0x08
#define RC1_RTO2        0x04
#define RC1_RTO1        0x02
#define RC1_RTO0        0x01



/* XPM0-2 (Transmit Pulse Mask 0-2)
   --------------------- E1 & T1 ------------------------- */

#define XPM0_XP12       0x80
#define XPM0_XP11       0x40
#define XPM0_XP10       0x20
#define XPM0_XP04       0x10
#define XPM0_XP03       0x08
#define XPM0_XP02       0x04
#define XPM0_XP01       0x02
#define XPM0_XP00       0x01

#define XPM1_XP30       0x80
#define XPM1_XP24       0x40
#define XPM1_XP23       0x20
#define XPM1_XP22       0x10
#define XPM1_XP21       0x08
#define XPM1_XP20       0x04
#define XPM1_XP14       0x02
#define XPM1_XP13       0x01

#define XPM2_XLHP       0x80
#define XPM2_XLT        0x40
#define XPM2_DAXLT      0x20
#define XPM2_XP34       0x08
#define XPM2_XP33       0x04
#define XPM2_XP32       0x02
#define XPM2_XP31       0x01


/* TSWM (Transparent Service Word Mask)
   ------------------ E1 ---------------------------- */

#define TSWM_TSIS       0x80
#define TSWM_TSIF       0x40
#define TSWM_TRA        0x20
#define TSWM_TSA4       0x10
#define TSWM_TSA5       0x08
#define TSWM_TSA6       0x04