xmac_ii.h

优龙2410linux2.6.8内核源代码

								/* Bit  4:	reserved */
#define XM_GP_RES_MAC	(1L<<3)	/* Bit  3: (sc)	Reset MAC and FIFOs */
#define XM_GP_RES_STAT	(1L<<2)	/* Bit  2: (sc)	Reset the statistics module */
								/* Bit  1:	reserved */
#define XM_GP_INP_ASS	(1L<<0)	/* Bit  0: (ro) GP Input Pin asserted */


/*	XM_IMSK		16 bit r/w	Interrupt Mask Register */
/*	XM_ISRC		16 bit r/o	Interrupt Status Register */
								/* Bit 15:	reserved */
#define XM_IS_LNK_AE	(1<<14) /* Bit 14:	Link Asynchronous Event */
#define XM_IS_TX_ABORT	(1<<13) /* Bit 13:	Transmit Abort, late Col. etc */
#define XM_IS_FRC_INT	(1<<12) /* Bit 12:	Force INT bit set in GP */
#define XM_IS_INP_ASS	(1<<11)	/* Bit 11:	Input Asserted, GP bit 0 set */
#define XM_IS_LIPA_RC	(1<<10)	/* Bit 10:	Link Partner requests config */
#define XM_IS_RX_PAGE	(1<<9)	/* Bit  9:	Page Received */
#define XM_IS_TX_PAGE	(1<<8)	/* Bit  8:	Next Page Loaded for Transmit */
#define XM_IS_AND		(1<<7)	/* Bit  7:	Auto-Negotiation Done */
#define XM_IS_TSC_OV	(1<<6)	/* Bit  6:	Time Stamp Counter Overflow */
#define XM_IS_RXC_OV	(1<<5)	/* Bit  5:	Rx Counter Event Overflow */
#define XM_IS_TXC_OV	(1<<4)	/* Bit  4:	Tx Counter Event Overflow */
#define XM_IS_RXF_OV	(1<<3)	/* Bit  3:	Receive FIFO Overflow */
#define XM_IS_TXF_UR	(1<<2)	/* Bit  2:	Transmit FIFO Underrun */
#define XM_IS_TX_COMP	(1<<1)	/* Bit  1:	Frame Tx Complete */
#define XM_IS_RX_COMP	(1<<0)	/* Bit  0:	Frame Rx Complete */

#define XM_DEF_MSK	(~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\
			XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR))


/*	XM_HW_CFG	16 bit r/w	Hardware Config Register */
								/* Bit 15.. 4:	reserved */
#define XM_HW_GEN_EOP	(1<<3)	/* Bit  3:	generate End of Packet pulse */
#define XM_HW_COM4SIG	(1<<2)	/* Bit  2:	use Comma Detect for Sig. Det.*/
								/* Bit  1:	reserved */
#define XM_HW_GMII_MD	(1<<0)	/* Bit  0:	GMII Interface selected */


/*	XM_TX_LO_WM	16 bit r/w	Tx FIFO Low Water Mark */
/*	XM_TX_HI_WM	16 bit r/w	Tx FIFO High Water Mark */
								/* Bit 15..10	reserved */
#define XM_TX_WM_MSK	0x01ff	/* Bit  9.. 0	Tx FIFO Watermark bits */

/*	XM_TX_THR	16 bit r/w	Tx Request Threshold */
/*	XM_HT_THR	16 bit r/w	Host Request Threshold */
/*	XM_RX_THR	16 bit r/w	Rx Request Threshold */
								/* Bit 15..11	reserved */
#define XM_THR_MSK		0x03ff	/* Bit 10.. 0	Rx/Tx Request Threshold bits */


/*	XM_TX_STAT	32 bit r/o	Tx Status LIFO Register */
#define XM_ST_VALID		(1UL<<31)	/* Bit 31:	Status Valid */
#define XM_ST_BYTE_CNT	(0x3fffL<<17)	/* Bit 30..17:	Tx frame Length */
#define XM_ST_RETRY_CNT	(0x1fL<<12)	/* Bit 16..12:	Retry Count */
#define XM_ST_EX_COL	(1L<<11)	/* Bit 11:	Excessive Collisions */
#define XM_ST_EX_DEF	(1L<<10)	/* Bit 10:	Excessive Deferral */
#define XM_ST_BURST		(1L<<9)		/* Bit  9:	p. xmitted in burst md*/
#define XM_ST_DEFER		(1L<<8)		/* Bit  8:	packet was defered */
#define XM_ST_BC		(1L<<7)		/* Bit  7:	Broadcast packet */
#define XM_ST_MC		(1L<<6)		/* Bit  6:	Multicast packet */
#define XM_ST_UC		(1L<<5)		/* Bit  5:	Unicast packet */
#define XM_ST_TX_UR		(1L<<4)		/* Bit  4:	FIFO Underrun occured */
#define XM_ST_CS_ERR	(1L<<3)		/* Bit  3:	Carrier Sense Error */
#define XM_ST_LAT_COL	(1L<<2)		/* Bit  2:	Late Collision Error */
#define XM_ST_MUL_COL	(1L<<1)		/* Bit  1:	Multiple Collisions */
#define XM_ST_SGN_COL	(1L<<0)		/* Bit  0:	Single Collision */

/*	XM_RX_LO_WM	16 bit r/w	Receive Low Water Mark */
/*	XM_RX_HI_WM	16 bit r/w	Receive High Water Mark */
									/* Bit 15..11:	reserved */
#define XM_RX_WM_MSK	0x03ff		/* Bit 11.. 0:	Rx FIFO Watermark bits */


/*	XM_DEV_ID	32 bit r/o	Device ID Register */
#define XM_DEV_OUI	(0x00ffffffUL<<8)	/* Bit 31..8:	Device OUI */
#define XM_DEV_REV	(0x07L << 5)		/* Bit  7..5:	Chip Rev Num */


/*	XM_MODE		32 bit r/w	Mode Register */
									/* Bit 31..27:	reserved */
#define XM_MD_ENA_REJ	(1L<<26)	/* Bit 26:	Enable Frame Reject */
#define XM_MD_SPOE_E	(1L<<25)	/* Bit 25:	Send Pause on Edge */
									/* 		extern generated */
#define XM_MD_TX_REP	(1L<<24)	/* Bit 24:	Transmit Repeater Mode */
#define XM_MD_SPOFF_I	(1L<<23)	/* Bit 23:	Send Pause on FIFO full */
									/*		intern generated */
#define XM_MD_LE_STW	(1L<<22)	/* Bit 22:	Rx Stat Word in Little Endian */
#define XM_MD_TX_CONT	(1L<<21)	/* Bit 21:	Send Continuous */
#define XM_MD_TX_PAUSE	(1L<<20)	/* Bit 20: (sc)	Send Pause Frame */
#define XM_MD_ATS		(1L<<19)	/* Bit 19:	Append Time Stamp */
#define XM_MD_SPOL_I	(1L<<18)	/* Bit 18:	Send Pause on Low */
									/*		intern generated */
#define XM_MD_SPOH_I	(1L<<17)	/* Bit 17:	Send Pause on High */
									/*		intern generated */
#define XM_MD_CAP		(1L<<16)	/* Bit 16:	Check Address Pair */
#define XM_MD_ENA_HASH	(1L<<15)	/* Bit 15:	Enable Hashing */
#define XM_MD_CSA		(1L<<14)	/* Bit 14:	Check Station Address */
#define XM_MD_CAA		(1L<<13)	/* Bit 13:	Check Address Array */
#define XM_MD_RX_MCTRL	(1L<<12)	/* Bit 12:	Rx MAC Control Frame */
#define XM_MD_RX_RUNT	(1L<<11)	/* Bit 11:	Rx Runt Frames */
#define XM_MD_RX_IRLE	(1L<<10)	/* Bit 10:	Rx in Range Len Err Frame */
#define XM_MD_RX_LONG	(1L<<9)		/* Bit  9:	Rx Long Frame */
#define XM_MD_RX_CRCE	(1L<<8)		/* Bit  8:	Rx CRC Error Frame */
#define XM_MD_RX_ERR	(1L<<7)		/* Bit  7:	Rx Error Frame */
#define XM_MD_DIS_UC	(1L<<6)		/* Bit  6:	Disable Rx Unicast */
#define XM_MD_DIS_MC	(1L<<5)		/* Bit  5:	Disable Rx Multicast */
#define XM_MD_DIS_BC	(1L<<4)		/* Bit  4:	Disable Rx Broadcast */
#define XM_MD_ENA_PROM	(1L<<3)		/* Bit  3:	Enable Promiscuous */
#define XM_MD_ENA_BE	(1L<<2)		/* Bit  2:	Enable Big Endian */
#define XM_MD_FTF		(1L<<1)		/* Bit  1: (sc)	Flush Tx FIFO */
#define XM_MD_FRF		(1L<<0)		/* Bit  0: (sc)	Flush Rx FIFO */

#define XM_PAUSE_MODE	(XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
#define XM_DEF_MODE		(XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
				XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)

/*	XM_STAT_CMD	16 bit r/w	Statistics Command Register */
								/* Bit 16..6:	reserved */
#define XM_SC_SNP_RXC	(1<<5)	/* Bit  5: (sc)	Snap Rx Counters */
#define XM_SC_SNP_TXC	(1<<4)	/* Bit  4: (sc)	Snap Tx Counters */
#define XM_SC_CP_RXC	(1<<3)	/* Bit  3: 	Copy Rx Counters Continuously */
#define XM_SC_CP_TXC	(1<<2)	/* Bit  2:	Copy Tx Counters Continuously */
#define XM_SC_CLR_RXC	(1<<1)	/* Bit  1: (sc)	Clear Rx Counters */
#define XM_SC_CLR_TXC	(1<<0)	/* Bit  0: (sc) Clear Tx Counters */


/*	XM_RX_CNT_EV	32 bit r/o	Rx Counter Event Register */
/*	XM_RX_EV_MSK	32 bit r/w	Rx Counter Event Mask */
#define XMR_MAX_SZ_OV	(1UL<<31)	/* Bit 31:	1024-MaxSize Rx Cnt Ov*/
#define XMR_1023B_OV	(1L<<30)	/* Bit 30:	512-1023Byte Rx Cnt Ov*/
#define XMR_511B_OV		(1L<<29)	/* Bit 29:	256-511 Byte Rx Cnt Ov*/
#define XMR_255B_OV		(1L<<28)	/* Bit 28:	128-255 Byte Rx Cnt Ov*/
#define XMR_127B_OV		(1L<<27)	/* Bit 27:	65-127 Byte Rx Cnt Ov */
#define XMR_64B_OV		(1L<<26)	/* Bit 26:	64 Byte Rx Cnt Ov */
#define XMR_UTIL_OV		(1L<<25)	/* Bit 25:	Rx Util Cnt Overflow */
#define XMR_UTIL_UR		(1L<<24)	/* Bit 24:	Rx Util Cnt Underrun */
#define XMR_CEX_ERR_OV	(1L<<23)	/* Bit 23:	CEXT Err Cnt Ov */
									/* Bit 22:	reserved */
#define XMR_FCS_ERR_OV	(1L<<21)	/* Bit 21:	Rx FCS Error Cnt Ov */
#define XMR_LNG_ERR_OV	(1L<<20)	/* Bit 20:	Rx too Long Err Cnt Ov*/
#define XMR_RUNT_OV		(1L<<19)	/* Bit 19:	Runt Event Cnt Ov */
#define XMR_SHT_ERR_OV	(1L<<18)	/* Bit 18:	Rx Short Ev Err Cnt Ov*/
#define XMR_SYM_ERR_OV	(1L<<17)	/* Bit 17:	Rx Sym Err Cnt Ov */
									/* Bit 16:	reserved */
#define XMR_CAR_ERR_OV	(1L<<15)	/* Bit 15:	Rx Carr Ev Err Cnt Ov */
#define XMR_JAB_PKT_OV	(1L<<14)	/* Bit 14:	Rx Jabb Packet Cnt Ov */
#define XMR_FIFO_OV		(1L<<13)	/* Bit 13:	Rx FIFO Ov Ev Cnt Ov */
#define XMR_FRA_ERR_OV	(1L<<12)	/* Bit 12:	Rx Framing Err Cnt Ov */
#define XMR_FMISS_OV	(1L<<11)	/* Bit 11:	Rx Missed Ev Cnt Ov */
#define XMR_BURST		(1L<<10)	/* Bit 10:	Rx Burst Event Cnt Ov */
#define XMR_INV_MOC		(1L<<9)		/* Bit  9:	Rx with inv. MAC OC Ov*/
#define XMR_INV_MP		(1L<<8)		/* Bit  8:	Rx inv Pause Frame Ov */
#define XMR_MCTRL_OV	(1L<<7)		/* Bit  7:	Rx MAC Ctrl-F Cnt Ov */
#define XMR_MPAUSE_OV	(1L<<6)		/* Bit  6:	Rx Pause MAC Ctrl-F Ov*/
#define XMR_UC_OK_OV	(1L<<5)		/* Bit  5:	Rx Unicast Frame CntOv*/
#define XMR_MC_OK_OV	(1L<<4)		/* Bit  4:	Rx Multicast Cnt Ov */
#define XMR_BC_OK_OV	(1L<<3)		/* Bit  3:	Rx Broadcast Cnt Ov */
#define XMR_OK_LO_OV	(1L<<2)		/* Bit  2:	Octets Rx OK Low CntOv*/
#define XMR_OK_HI_OV	(1L<<1)		/* Bit  1:	Octets Rx OK Hi Cnt Ov*/
#define XMR_OK_OV		(1L<<0)		/* Bit  0:	Frames Received Ok Ov */

#define XMR_DEF_MSK		(XMR_OK_LO_OV | XMR_OK_HI_OV)

/*	XM_TX_CNT_EV	32 bit r/o	Tx Counter Event Register */
/*	XM_TX_EV_MSK	32 bit r/w	Tx Counter Event Mask */
									/* Bit 31..26:	reserved */
#define XMT_MAX_SZ_OV	(1L<<25)	/* Bit 25:	1024-MaxSize Tx Cnt Ov*/
#define XMT_1023B_OV	(1L<<24)	/* Bit 24:	512-1023Byte Tx Cnt Ov*/
#define XMT_511B_OV		(1L<<23)	/* Bit 23:	256-511 Byte Tx Cnt Ov*/
#define XMT_255B_OV		(1L<<22)	/* Bit 22:	128-255 Byte Tx Cnt Ov*/
#define XMT_127B_OV		(1L<<21)	/* Bit 21:	65-127 Byte Tx Cnt Ov */
#define XMT_64B_OV		(1L<<20)	/* Bit 20:	64 Byte Tx Cnt Ov */
#define XMT_UTIL_OV		(1L<<19)	/* Bit 19:	Tx Util Cnt Overflow */
#define XMT_UTIL_UR		(1L<<18)	/* Bit 18:	Tx Util Cnt Underrun */
#define XMT_CS_ERR_OV	(1L<<17)	/* Bit 17:	Tx Carr Sen Err Cnt Ov*/
#define XMT_FIFO_UR_OV	(1L<<16)	/* Bit 16:	Tx FIFO Ur Ev Cnt Ov */
#define XMT_EX_DEF_OV	(1L<<15)	/* Bit 15:	Tx Ex Deferall Cnt Ov */
#define XMT_DEF			(1L<<14)	/* Bit 14:	Tx Deferred Cnt Ov */
#define XMT_LAT_COL_OV	(1L<<13)	/* Bit 13:	Tx Late Col Cnt Ov */
#define XMT_ABO_COL_OV	(1L<<12)	/* Bit 12:	Tx abo dueto Ex Col Ov*/
#define XMT_MUL_COL_OV	(1L<<11)	/* Bit 11:	Tx Mult Col Cnt Ov */
#define XMT_SNG_COL		(1L<<10)	/* Bit 10:	Tx Single Col Cnt Ov */
#define XMT_MCTRL_OV	(1L<<9)		/* Bit  9:	Tx MAC Ctrl Counter Ov*/
#define XMT_MPAUSE		(1L<<8)		/* Bit  8:	Tx Pause MAC Ctrl-F Ov*/
#define XMT_BURST		(1L<<7)		/* Bit  7:	Tx Burst Event Cnt Ov */
#define XMT_LONG		(1L<<6)		/* Bit  6:	Tx Long Frame Cnt Ov */
#define XMT_UC_OK_OV	(1L<<5)		/* Bit  5:	Tx Unicast Cnt Ov */
#define XMT_MC_OK_OV	(1L<<4)		/* Bit  4:	Tx Multicast Cnt Ov */
#define XMT_BC_OK_OV	(1L<<3)		/* Bit  3:	Tx Broadcast Cnt Ov */
#define XMT_OK_LO_OV	(1L<<2)		/* Bit  2:	Octets Tx OK Low CntOv*/
#define XMT_OK_HI_OV	(1L<<1)		/* Bit  1:	Octets Tx OK Hi Cnt Ov*/
#define XMT_OK_OV		(1L<<0)		/* Bit  0:	Frames Tx Ok Ov */

#define XMT_DEF_MSK		(XMT_OK_LO_OV | XMT_OK_HI_OV)

/*
 * Receive Frame Status Encoding
 */
#define XMR_FS_LEN	(0x3fffUL<<18)	/* Bit 31..18:	Rx Frame Length */
#define XMR_FS_2L_VLAN	(1L<<17)	/* Bit 17:	tagged wh 2Lev VLAN ID*/
#define XMR_FS_1L_VLAN	(1L<<16)	/* Bit 16:	tagged wh 1Lev VLAN ID*/
#define XMR_FS_BC		(1L<<15)	/* Bit 15:	Broadcast Frame */
#define XMR_FS_MC		(1L<<14)	/* Bit 14:	Multicast Frame */
#define XMR_FS_UC		(1L<<13)	/* Bit 13:	Unicast Frame */
									/* Bit 12:	reserved */
#define XMR_FS_BURST	(1L<<11)	/* Bit 11:	Burst Mode */
#define XMR_FS_CEX_ERR	(1L<<10)	/* Bit 10:	Carrier Ext. Error */
#define XMR_FS_802_3	(1L<<9)		/* Bit  9:	802.3 Frame */
#define XMR_FS_COL_ERR	(1L<<8)		/* Bit  8:	Collision Error */
#define XMR_FS_CAR_ERR	(1L<<7)		/* Bit  7:	Carrier Event Error */
#define XMR_FS_LEN_ERR	(1L<<6)		/* Bit  6:	In-Range Length Error */
#define XMR_FS_FRA_ERR	(1L<<5)		/* Bit  5:	Framing Error */
#define XMR_FS_RUNT		(1L<<4)		/* Bit  4:	Runt Frame */
#define XMR_FS_LNG_ERR	(1L<<3)		/* Bit  3:	Giant (Jumbo) Frame */
#define XMR_FS_FCS_ERR	(1L<<2)		/* Bit  2:	Frame Check Sequ Err */
#define XMR_FS_ERR		(1L<<1)		/* Bit  1:	Frame Error */
#define XMR_FS_MCTRL	(1L<<0)		/* Bit  0:	MAC Control Packet */

/*
 * XMR_FS_ERR will be set if
 *	XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
 *	XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
 * XMR_FS_ERR unless the corresponding bit in the Receive Command
 * Register is set.
 */
#define XMR_FS_ANY_ERR	XMR_FS_ERR

/*----------------------------------------------------------------------------*/
/*
 * XMAC-PHY Registers, indirect addressed over the XMAC
 */
#define PHY_XMAC_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define PHY_XMAC_STAT		0x01	/* 16 bit r/w	PHY Status Register */
#define PHY_XMAC_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
#define PHY_XMAC_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
#define PHY_XMAC_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
#define PHY_XMAC_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Abi Reg */
#define PHY_XMAC_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
#define PHY_XMAC_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define PHY_XMAC_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
	/* 0x09 - 0x0e:		reserved */
#define PHY_XMAC_EXT_STAT	0x0f	/* 16 bit r/o	Ext Status Register */
#define PHY_XMAC_RES_ABI	0x10	/* 16 bit r/o	PHY Resolved Ability */

/*----------------------------------------------------------------------------*/
/*
 * Broadcom-PHY Registers, indirect addressed over XMAC
 */
#define PHY_BCOM_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define PHY_BCOM_STAT		0x01	/* 16 bit r/o	PHY Status Register */
#define PHY_BCOM_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
#define PHY_BCOM_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */