xmac_ii.h

优龙2410linux2.6.8内核源代码

/******************************************************************************
 *
 * Name:	xmac_ii.h
 * Project:	Gigabit Ethernet Adapters, Common Modules
 * Version:	$Revision: 1.52 $
 * Date:	$Date: 2003/10/02 16:35:50 $
 * Purpose:	Defines and Macros for Gigabit Ethernet Controller
 *
 ******************************************************************************/

/******************************************************************************
 *
 *	(C)Copyright 1998-2002 SysKonnect.
 *	(C)Copyright 2002-2003 Marvell.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

#ifndef __INC_XMAC_H
#define __INC_XMAC_H

#ifdef __cplusplus
extern "C" {
#endif	/* __cplusplus */

/* defines ********************************************************************/

/*
 * XMAC II registers
 *
 * The XMAC registers are 16 or 32 bits wide.
 * The XMACs host processor interface is set to 16 bit mode,
 * therefore ALL registers will be addressed with 16 bit accesses.
 *
 * The following macros are provided to access the XMAC registers
 * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(),
 * XM_INHASH(), and XM_OUTHASH().
 * The macros are defined in SkGeHw.h.
 *
 * Note:	NA reg	= Network Address e.g DA, SA etc.
 *
 */
#define XM_MMU_CMD		0x0000	/* 16 bit r/w	MMU Command Register */
	/* 0x0004:		reserved */
#define XM_POFF			0x0008	/* 32 bit r/w	Packet Offset Register */
#define XM_BURST		0x000c	/* 32 bit r/w	Burst Register for half duplex*/
#define XM_1L_VLAN_TAG	0x0010	/* 16 bit r/w	One Level VLAN Tag ID */
#define XM_2L_VLAN_TAG	0x0014	/* 16 bit r/w	Two Level VLAN Tag ID */
	/* 0x0018 - 0x001e:	reserved */
#define XM_TX_CMD		0x0020	/* 16 bit r/w	Transmit Command Register */
#define XM_TX_RT_LIM	0x0024	/* 16 bit r/w	Transmit Retry Limit Register */
#define XM_TX_STIME		0x0028	/* 16 bit r/w	Transmit Slottime Register */
#define XM_TX_IPG		0x002c	/* 16 bit r/w	Transmit Inter Packet Gap */
#define XM_RX_CMD		0x0030	/* 16 bit r/w	Receive Command Register */
#define XM_PHY_ADDR		0x0034	/* 16 bit r/w	PHY Address Register */
#define XM_PHY_DATA		0x0038	/* 16 bit r/w	PHY Data Register */
	/* 0x003c: 		reserved */
#define XM_GP_PORT		0x0040	/* 32 bit r/w	General Purpose Port Register */
#define XM_IMSK			0x0044	/* 16 bit r/w	Interrupt Mask Register */
#define XM_ISRC			0x0048	/* 16 bit r/o	Interrupt Status Register */
#define XM_HW_CFG		0x004c	/* 16 bit r/w	Hardware Config Register */
	/* 0x0050 - 0x005e:	reserved */
#define XM_TX_LO_WM		0x0060	/* 16 bit r/w	Tx FIFO Low Water Mark */
#define XM_TX_HI_WM		0x0062	/* 16 bit r/w	Tx FIFO High Water Mark */
#define XM_TX_THR		0x0064	/* 16 bit r/w	Tx Request Threshold */
#define XM_HT_THR		0x0066	/* 16 bit r/w	Host Request Threshold */
#define XM_PAUSE_DA		0x0068	/* NA reg r/w	Pause Destination Address */
	/* 0x006e: 		reserved */
#define XM_CTL_PARA		0x0070	/* 32 bit r/w	Control Parameter Register */
#define XM_MAC_OPCODE	0x0074	/* 16 bit r/w	Opcode for MAC control frames */
#define XM_MAC_PTIME	0x0076	/* 16 bit r/w	Pause time for MAC ctrl frames*/
#define XM_TX_STAT		0x0078	/* 32 bit r/o	Tx Status LIFO Register */

	/* 0x0080 - 0x00fc:	16 NA reg r/w	Exact Match Address Registers */
	/* 				use the XM_EXM() macro to address */
#define XM_EXM_START	0x0080	/* r/w	Start Address of the EXM Regs */

	/*
	 * XM_EXM(Reg)
	 *
	 * returns the XMAC address offset of specified Exact Match Addr Reg
	 *
	 * para:	Reg	EXM register to addr	(0 .. 15)
	 *
	 * usage:	XM_INADDR(IoC, MAC_1, XM_EXM(i), &val[i]);
	 */
#define XM_EXM(Reg)	(XM_EXM_START + ((Reg) << 3))

#define XM_SRC_CHK		0x0100	/* NA reg r/w	Source Check Address Register */
#define XM_SA			0x0108	/* NA reg r/w	Station Address Register */
#define XM_HSM			0x0110	/* 64 bit r/w	Hash Match Address Registers */
#define XM_RX_LO_WM		0x0118	/* 16 bit r/w	Receive Low Water Mark */
#define XM_RX_HI_WM		0x011a	/* 16 bit r/w	Receive High Water Mark */
#define XM_RX_THR		0x011c	/* 32 bit r/w	Receive Request Threshold */
#define XM_DEV_ID		0x0120	/* 32 bit r/o	Device ID Register */
#define XM_MODE			0x0124	/* 32 bit r/w	Mode Register */
#define XM_LSA			0x0128	/* NA reg r/o	Last Source Register */
	/* 0x012e:		reserved */
#define XM_TS_READ		0x0130	/* 32 bit r/o	Time Stamp Read Register */
#define XM_TS_LOAD		0x0134	/* 32 bit r/o	Time Stamp Load Value */
	/* 0x0138 - 0x01fe:	reserved */
#define XM_STAT_CMD	0x0200	/* 16 bit r/w	Statistics Command Register */
#define XM_RX_CNT_EV	0x0204	/* 32 bit r/o	Rx Counter Event Register */
#define XM_TX_CNT_EV	0x0208	/* 32 bit r/o	Tx Counter Event Register */
#define XM_RX_EV_MSK	0x020c	/* 32 bit r/w	Rx Counter Event Mask */
#define XM_TX_EV_MSK	0x0210	/* 32 bit r/w	Tx Counter Event Mask */
	/* 0x0204 - 0x027e:	reserved */
#define XM_TXF_OK		0x0280	/* 32 bit r/o	Frames Transmitted OK Conuter */
#define XM_TXO_OK_HI	0x0284	/* 32 bit r/o	Octets Transmitted OK High Cnt*/
#define XM_TXO_OK_LO	0x0288	/* 32 bit r/o	Octets Transmitted OK Low Cnt */
#define XM_TXF_BC_OK	0x028c	/* 32 bit r/o	Broadcast Frames Xmitted OK */
#define XM_TXF_MC_OK	0x0290	/* 32 bit r/o	Multicast Frames Xmitted OK */
#define XM_TXF_UC_OK	0x0294	/* 32 bit r/o	Unicast Frames Xmitted OK */
#define XM_TXF_LONG		0x0298	/* 32 bit r/o	Tx Long Frame Counter */
#define XM_TXE_BURST	0x029c	/* 32 bit r/o	Tx Burst Event Counter */
#define XM_TXF_MPAUSE	0x02a0	/* 32 bit r/o	Tx Pause MAC Ctrl Frame Cnt */
#define XM_TXF_MCTRL	0x02a4	/* 32 bit r/o	Tx MAC Ctrl Frame Counter */
#define XM_TXF_SNG_COL	0x02a8	/* 32 bit r/o	Tx Single Collision Counter */
#define XM_TXF_MUL_COL	0x02ac	/* 32 bit r/o	Tx Multiple Collision Counter */
#define XM_TXF_ABO_COL	0x02b0	/* 32 bit r/o	Tx aborted due to Exces. Col. */
#define XM_TXF_LAT_COL	0x02b4	/* 32 bit r/o	Tx Late Collision Counter */
#define XM_TXF_DEF		0x02b8	/* 32 bit r/o	Tx Deferred Frame Counter */
#define XM_TXF_EX_DEF	0x02bc	/* 32 bit r/o	Tx Excessive Deferall Counter */
#define XM_TXE_FIFO_UR	0x02c0	/* 32 bit r/o	Tx FIFO Underrun Event Cnt */
#define XM_TXE_CS_ERR	0x02c4	/* 32 bit r/o	Tx Carrier Sense Error Cnt */
#define XM_TXP_UTIL		0x02c8	/* 32 bit r/o	Tx Utilization in % */
	/* 0x02cc - 0x02ce:	reserved */
#define XM_TXF_64B		0x02d0	/* 32 bit r/o	64 Byte Tx Frame Counter */
#define XM_TXF_127B		0x02d4	/* 32 bit r/o	65-127 Byte Tx Frame Counter */
#define XM_TXF_255B		0x02d8	/* 32 bit r/o	128-255 Byte Tx Frame Counter */
#define XM_TXF_511B		0x02dc	/* 32 bit r/o	256-511 Byte Tx Frame Counter */
#define XM_TXF_1023B	0x02e0	/* 32 bit r/o	512-1023 Byte Tx Frame Counter*/
#define XM_TXF_MAX_SZ	0x02e4	/* 32 bit r/o	1024-MaxSize Byte Tx Frame Cnt*/
	/* 0x02e8 - 0x02fe:	reserved */
#define XM_RXF_OK		0x0300	/* 32 bit r/o	Frames Received OK */
#define XM_RXO_OK_HI	0x0304	/* 32 bit r/o	Octets Received OK High Cnt */
#define XM_RXO_OK_LO	0x0308	/* 32 bit r/o	Octets Received OK Low Counter*/
#define XM_RXF_BC_OK	0x030c	/* 32 bit r/o	Broadcast Frames Received OK */
#define XM_RXF_MC_OK	0x0310	/* 32 bit r/o	Multicast Frames Received OK */
#define XM_RXF_UC_OK	0x0314	/* 32 bit r/o	Unicast Frames Received OK */
#define XM_RXF_MPAUSE	0x0318	/* 32 bit r/o	Rx Pause MAC Ctrl Frame Cnt */
#define XM_RXF_MCTRL	0x031c	/* 32 bit r/o	Rx MAC Ctrl Frame Counter */
#define XM_RXF_INV_MP	0x0320	/* 32 bit r/o	Rx invalid Pause Frame Cnt */
#define XM_RXF_INV_MOC	0x0324	/* 32 bit r/o	Rx Frames with inv. MAC Opcode*/
#define XM_RXE_BURST	0x0328	/* 32 bit r/o	Rx Burst Event Counter */
#define XM_RXE_FMISS	0x032c	/* 32 bit r/o	Rx Missed Frames Event Cnt */
#define XM_RXF_FRA_ERR	0x0330	/* 32 bit r/o	Rx Framing Error Counter */
#define XM_RXE_FIFO_OV	0x0334	/* 32 bit r/o	Rx FIFO overflow Event Cnt */
#define XM_RXF_JAB_PKT	0x0338	/* 32 bit r/o	Rx Jabber Packet Frame Cnt */
#define XM_RXE_CAR_ERR	0x033c	/* 32 bit r/o	Rx Carrier Event Error Cnt */
#define XM_RXF_LEN_ERR	0x0340	/* 32 bit r/o	Rx in Range Length Error */
#define XM_RXE_SYM_ERR	0x0344	/* 32 bit r/o	Rx Symbol Error Counter */
#define XM_RXE_SHT_ERR	0x0348	/* 32 bit r/o	Rx Short Event Error Cnt */
#define XM_RXE_RUNT		0x034c	/* 32 bit r/o	Rx Runt Event Counter */
#define XM_RXF_LNG_ERR	0x0350	/* 32 bit r/o	Rx Frame too Long Error Cnt */
#define XM_RXF_FCS_ERR	0x0354	/* 32 bit r/o	Rx Frame Check Seq. Error Cnt */
	/* 0x0358 - 0x035a:	reserved */
#define XM_RXF_CEX_ERR	0x035c	/* 32 bit r/o	Rx Carrier Ext Error Frame Cnt*/
#define XM_RXP_UTIL		0x0360	/* 32 bit r/o	Rx Utilization in % */
	/* 0x0364 - 0x0366:	reserved */
#define XM_RXF_64B		0x0368	/* 32 bit r/o	64 Byte Rx Frame Counter */
#define XM_RXF_127B		0x036c	/* 32 bit r/o	65-127 Byte Rx Frame Counter */
#define XM_RXF_255B		0x0370	/* 32 bit r/o	128-255 Byte Rx Frame Counter */
#define XM_RXF_511B		0x0374	/* 32 bit r/o	256-511 Byte Rx Frame Counter */
#define XM_RXF_1023B	0x0378	/* 32 bit r/o	512-1023 Byte Rx Frame Counter*/
#define XM_RXF_MAX_SZ	0x037c	/* 32 bit r/o	1024-MaxSize Byte Rx Frame Cnt*/
	/* 0x02e8 - 0x02fe:	reserved */


/*----------------------------------------------------------------------------*/
/*
 * XMAC Bit Definitions
 *
 * If the bit access behaviour differs from the register access behaviour
 * (r/w, r/o) this is documented after the bit number.
 * The following bit access behaviours are used:
 *	(sc)	self clearing
 *	(ro)	read only
 */

/*	XM_MMU_CMD	16 bit r/w	MMU Command Register */
								/* Bit 15..13:	reserved */
#define XM_MMU_PHY_RDY	(1<<12)	/* Bit 12:	PHY Read Ready */
#define XM_MMU_PHY_BUSY	(1<<11)	/* Bit 11:	PHY Busy */
#define XM_MMU_IGN_PF	(1<<10)	/* Bit 10:	Ignore Pause Frame */
#define XM_MMU_MAC_LB	(1<<9)	/* Bit  9:	Enable MAC Loopback */
								/* Bit  8:	reserved */
#define XM_MMU_FRC_COL	(1<<7)	/* Bit  7:	Force Collision */
#define XM_MMU_SIM_COL	(1<<6)	/* Bit  6:	Simulate Collision */
#define XM_MMU_NO_PRE	(1<<5)	/* Bit  5:	No MDIO Preamble */
#define XM_MMU_GMII_FD	(1<<4)	/* Bit  4:	GMII uses Full Duplex */
#define XM_MMU_RAT_CTRL	(1<<3)	/* Bit  3:	Enable Rate Control */
#define XM_MMU_GMII_LOOP (1<<2)	/* Bit  2:	PHY is in Loopback Mode */
#define XM_MMU_ENA_RX	(1<<1)	/* Bit  1:	Enable Receiver */
#define XM_MMU_ENA_TX	(1<<0)	/* Bit  0:	Enable Transmitter */


/*	XM_TX_CMD	16 bit r/w	Transmit Command Register */
								/* Bit 15..7:	reserved */
#define XM_TX_BK2BK		(1<<6)	/* Bit  6:	Ignor Carrier Sense (Tx Bk2Bk)*/
#define XM_TX_ENC_BYP	(1<<5)	/* Bit  5:	Set Encoder in Bypass Mode */
#define XM_TX_SAM_LINE	(1<<4)	/* Bit  4: (sc)	Start utilization calculation */
#define XM_TX_NO_GIG_MD	(1<<3)	/* Bit  3:	Disable Carrier Extension */
#define XM_TX_NO_PRE	(1<<2)	/* Bit  2:	Disable Preamble Generation */
#define XM_TX_NO_CRC	(1<<1)	/* Bit  1:	Disable CRC Generation */
#define XM_TX_AUTO_PAD	(1<<0)	/* Bit  0:	Enable Automatic Padding */


/*	XM_TX_RT_LIM	16 bit r/w	Transmit Retry Limit Register */
								/* Bit 15..5:	reserved */
#define XM_RT_LIM_MSK	0x1f	/* Bit  4..0:	Tx Retry Limit */


/*	XM_TX_STIME	16 bit r/w	Transmit Slottime Register */
								/* Bit 15..7:	reserved */
#define XM_STIME_MSK	0x7f	/* Bit  6..0:	Tx Slottime bits */


/*	XM_TX_IPG	16 bit r/w	Transmit Inter Packet Gap */
								/* Bit 15..8:	reserved */
#define XM_IPG_MSK		0xff	/* Bit  7..0:	IPG value bits */


/*	XM_RX_CMD	16 bit r/w	Receive Command Register */
								/* Bit 15..9:	reserved */
#define XM_RX_LENERR_OK (1<<8)	/* Bit  8	don't set Rx Err bit for */
								/*		inrange error packets */
#define XM_RX_BIG_PK_OK	(1<<7)	/* Bit  7	don't set Rx Err bit for */
								/*		jumbo packets */
#define XM_RX_IPG_CAP	(1<<6)	/* Bit  6	repl. type field with IPG */
#define XM_RX_TP_MD		(1<<5)	/* Bit  5:	Enable transparent Mode */
#define XM_RX_STRIP_FCS	(1<<4)	/* Bit  4:	Enable FCS Stripping */
#define XM_RX_SELF_RX	(1<<3)	/* Bit  3: 	Enable Rx of own packets */
#define XM_RX_SAM_LINE	(1<<2)	/* Bit  2: (sc)	Start utilization calculation */
#define XM_RX_STRIP_PAD	(1<<1)	/* Bit  1:	Strip pad bytes of Rx frames */
#define XM_RX_DIS_CEXT	(1<<0)	/* Bit  0:	Disable carrier ext. check */


/*	XM_PHY_ADDR	16 bit r/w	PHY Address Register */
								/* Bit 15..5:	reserved */
#define XM_PHY_ADDR_SZ	0x1f	/* Bit  4..0:	PHY Address bits */


/*	XM_GP_PORT	32 bit r/w	General Purpose Port Register */
								/* Bit 31..7:	reserved */
#define XM_GP_ANIP		(1L<<6)	/* Bit  6: (ro)	Auto-Neg. in progress */
#define XM_GP_FRC_INT	(1L<<5)	/* Bit  5: (sc)	Force Interrupt */