📄 smc91x.c
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SMC_SET_PTR( PTR_AUTOINC ); buf = skb->data; len = skb->len; PRINTK2("%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", dev->name, packet_no, len, len, buf); PRINT_PKT(buf, len); /* * Send the packet length ( +6 for status words, length, and ctl. * The card will pad to 64 bytes with zeroes if packet is too small. */ SMC_PUT_PKT_HDR(0, len + 6); /* send the actual data */ SMC_PUSH_DATA(buf, len & ~1); /* Send final ctl word with the last byte if there is one */ SMC_outw( ((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG ); /* and let the chipset deal with it */ SMC_SET_MMU_CMD( MC_ENQUEUE ); SMC_ACK_INT( IM_TX_EMPTY_INT ); dev->trans_start = jiffies; dev_kfree_skb_any(skb); lp->saved_skb = NULL; lp->stats.tx_packets++; lp->stats.tx_bytes += len;}/* . Since I am not sure if I will have enough room in the chip's ram . to store the packet, I call this routine which either sends it . now, or set the card to generates an interrupt when ready . for the packet. */static intsmc_hard_start_xmit( struct sk_buff * skb, struct net_device * dev ){ struct smc_local *lp = (struct smc_local *)dev->priv; unsigned long ioaddr = dev->base_addr; unsigned int numPages, poll_count, status, saved_bank; PRINTK3("%s: %s\n", dev->name, __FUNCTION__); if (unlikely(lp->saved_skb != NULL)) { /* THIS SHOULD NEVER HAPPEN. */ printk( KERN_CRIT "%s: Bad Craziness - sent packet while busy.\n", dev->name ); lp->stats.tx_errors++; lp->stats.tx_aborted_errors++; return 1; } lp->saved_skb = skb; /* ** The MMU wants the number of pages to be the number of 256 bytes ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) ** ** The 91C111 ignores the size bits, but the code is left intact ** for backwards and future compatibility. ** ** Pkt size for allocating is data length +6 (for additional status ** words, length and ctl!) ** ** If odd size then last byte is included in ctl word. */ numPages = ((skb->len & ~1) + (6 - 1)) >> 8; if (unlikely(numPages > 7)) { printk("%s: Far too big packet error.\n", dev->name); lp->saved_skb = NULL; lp->stats.tx_errors++; lp->stats.tx_dropped++; dev_kfree_skb(skb); return 0; } /* now, try to allocate the memory */ saved_bank = SMC_CURRENT_BANK(); SMC_SELECT_BANK( 2 ); SMC_SET_MMU_CMD( MC_ALLOC | numPages ); /* * Poll the chip for a short amount of time in case the * allocation succeeds quickly. */ poll_count = MEMORY_WAIT_TIME; do { status = SMC_GET_INT(); if (status & IM_ALLOC_INT) { SMC_ACK_INT( IM_ALLOC_INT ); break; } } while (--poll_count); if (!poll_count) { /* oh well, wait until the chip finds memory later */ netif_stop_queue(dev); PRINTK2("%s: TX memory allocation deferred.\n", dev->name); SMC_ENABLE_INT( IM_ALLOC_INT ); } else { /* Send current packet immediately.. */#if THROTTLE_TX_PKTS netif_stop_queue(dev);#endif smc_hardware_send_packet(dev); SMC_ENABLE_INT( IM_TX_INT | IM_TX_EMPTY_INT ); } SMC_SELECT_BANK( saved_bank ); return 0;}/* . This handles a TX interrupt, which is only called when an error . relating to a packet is sent or CTL_AUTO_RELEASE is not set.*/static voidsmc_tx(struct net_device *dev){ unsigned long ioaddr = dev->base_addr; struct smc_local *lp = (struct smc_local *)dev->priv; unsigned int saved_packet, packet_no, tx_status, pkt_len; PRINTK3("%s: %s\n", dev->name, __FUNCTION__); /* If the TX FIFO is empty then nothing to do */ packet_no = SMC_GET_TXFIFO(); if (unlikely(packet_no & TXFIFO_TEMPTY)) { PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); return; } /* select packet to read from */ saved_packet = SMC_GET_PN(); SMC_SET_PN( packet_no ); /* read the first word (status word) from this packet */ SMC_SET_PTR( PTR_AUTOINC | PTR_READ ); SMC_GET_PKT_HDR(tx_status, pkt_len); PRINTK2("%s: TX STATUS 0x%04x PNR 0x%02x\n", dev->name, tx_status, packet_no); if (!(tx_status & TS_SUCCESS)) lp->stats.tx_errors++; if (tx_status & TS_LOSTCAR) lp->stats.tx_carrier_errors++; if (tx_status & TS_LATCOL) { printk( KERN_DEBUG "%s: Late collision occurred on last xmit.\n", dev->name); lp->stats.tx_window_errors++; } /* kill the packet */ SMC_WAIT_MMU_BUSY(); SMC_SET_MMU_CMD( MC_FREEPKT ); /* Don't restore Packet Number Reg until busy bit is cleared */ SMC_WAIT_MMU_BUSY(); SMC_SET_PN( saved_packet ); /* re-enable transmit */ SMC_SELECT_BANK( 0 ); SMC_SET_TCR( lp->tcr_cur_mode ); SMC_SELECT_BANK( 2 );}//---PHY CONTROL AND CONFIGURATION-----------------------------------------static void smc_mii_out(struct net_device *dev, unsigned int val, int bits){ unsigned long ioaddr = dev->base_addr; unsigned int mii_reg, mask; mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); mii_reg |= MII_MDOE; for (mask = 1 << (bits - 1); mask; mask >>= 1) { if (val & mask) mii_reg |= MII_MDO; else mii_reg &= ~MII_MDO; SMC_SET_MII(mii_reg); udelay(MII_DELAY); SMC_SET_MII(mii_reg | MII_MCLK); udelay(MII_DELAY); }}static unsigned int smc_mii_in(struct net_device *dev, int bits){ unsigned long ioaddr = dev->base_addr; unsigned int mii_reg, mask, val; mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); SMC_SET_MII(mii_reg); for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { if (SMC_GET_MII() & MII_MDI) val |= mask; SMC_SET_MII(mii_reg); udelay(MII_DELAY); SMC_SET_MII(mii_reg | MII_MCLK); udelay(MII_DELAY); } return val;}/*------------------------------------------------------------ . Reads a register from the MII Management serial interface .-------------------------------------------------------------*/static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg){ unsigned long ioaddr = dev->base_addr; unsigned int phydata, old_bank; // Save the current bank, and select bank 3 old_bank = SMC_CURRENT_BANK(); SMC_SELECT_BANK(3); // Idle - 32 ones smc_mii_out(dev, 0xffffffff, 32); // Start code (01) + read (10) + phyaddr + phyreg smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); // Turnaround (2bits) + phydata phydata = smc_mii_in(dev, 18); // Return to idle state SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); // And select original bank SMC_SELECT_BANK(old_bank); PRINTK3("%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", __FUNCTION__, phyaddr, phyreg, phydata); return phydata;}/*------------------------------------------------------------ . Writes a register to the MII Management serial interface .-------------------------------------------------------------*/static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, int phydata){ unsigned long ioaddr = dev->base_addr; unsigned int old_bank; // Save the current bank, and select bank 3 old_bank = SMC_CURRENT_BANK(); SMC_SELECT_BANK(3); // Idle - 32 ones smc_mii_out(dev, 0xffffffff, 32); // Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); // Return to idle state SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); // And select original bank SMC_SELECT_BANK(old_bank); PRINTK3("%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", __FUNCTION__, phyaddr, phyreg, phydata);}/*------------------------------------------------------------ . Finds and reports the PHY address .-------------------------------------------------------------*/static void smc_detect_phy(struct net_device* dev){ struct smc_local *lp = (struct smc_local *)dev->priv; int phyaddr; PRINTK2("%s: %s\n", dev->name, __FUNCTION__); lp->phy_type = 0; // Scan all 32 PHY addresses if necessary for (phyaddr = 0; phyaddr < 32; ++phyaddr) { unsigned int id1, id2; // Read the PHY identifiers id1 = smc_phy_read(dev, phyaddr, MII_PHYSID1); id2 = smc_phy_read(dev, phyaddr, MII_PHYSID2); PRINTK3("%s: phy_id1=0x%x, phy_id2=0x%x\n", dev->name, id1, id2); // Make sure it is a valid identifier if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { // Save the PHY's address lp->mii.phy_id = phyaddr; lp->phy_type = id1 << 16 | id2; break; } } if (lp->phy_type == 0) { PRINTK("%s: No PHY found\n", dev->name); return; } // Set the PHY type if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { PRINTK("%s: PHY=LAN83C183 (LAN91C111 Internal)\n", dev->name); } if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { PRINTK("%s: PHY=LAN83C180\n", dev->name); }}/*------------------------------------------------------------ . Waits the specified number of milliseconds - kernel friendly .-------------------------------------------------------------*/static voidsmc_wait_ms(unsigned int ms){ if (!in_interrupt()) { set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(1 + ms * HZ / 1000); } else { /* if this happens it must be fixed */ printk( KERN_WARNING "%s: busy wait while in interrupt!\n", __FUNCTION__); mdelay(ms); }}/*------------------------------------------------------------ . Sets the PHY to a configuration as determined by the user .-------------------------------------------------------------*/static intsmc_phy_fixed(struct net_device *dev){ struct smc_local *lp = (struct smc_local *)dev->priv; unsigned long ioaddr = dev->base_addr; int phyaddr = lp->mii.phy_id; int bmcr, cfg1; PRINTK3("%s: %s\n", dev->name, __FUNCTION__); // Enter Link Disable state cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); cfg1 |= PHY_CFG1_LNKDIS; smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); // Set our fixed capabilities // Disable auto-negotiation bmcr = 0; if (lp->ctl_rfduplx) bmcr |= BMCR_FULLDPLX; if (lp->ctl_rspeed == 100) bmcr |= BMCR_SPEED100; // Write our capabilities to the phy control register smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); // Re-Configure the Receive/Phy Control register SMC_SET_RPC( lp->rpc_cur_mode ); // Success return(1);}/* * smc_phy_reset - reset the phy * @dev: net device * @phy: phy address * * Issue a software reset for the specified PHY and * wait up to 100ms for the reset to complete. We should * not access the PHY for 50ms after issuing the reset. * * The time to wait appears to be dependent on the PHY. * * Must be called with lp->lock locked. */static int smc_phy_reset(struct net_device *dev, int phy){ struct smc_local *lp = (struct smc_local *)dev->priv; unsigned int bmcr; int timeout; smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); for (timeout = 2; timeout; timeout--) { spin_unlock_irq(&lp->lock); smc_wait_ms(50); spin_lock_irq(&lp->lock); bmcr = smc_phy_read(dev, phy, MII_BMCR); if (!(bmcr & BMCR_RESET)) break; } return bmcr & BMCR_RESET;}/* * smc_phy_powerdown - powerdown phy * @dev: net device * @phy: phy address * * Power down the specified PHY */static void smc_phy_powerdown(struct net_device *dev, int phy){ unsigned int bmcr; bmcr = smc_phy_read(dev, phy, MII_BMCR); smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);}/* * smc_phy_check_media - check the media status and adjust TCR * @dev: net device * @init: set true for initialisation * * Select duplex mode depending on negotiation state. This * also updates our carrier state. */static void smc_phy_check_media(struct net_device *dev, int init){ struct smc_local *lp = (struct smc_local *)dev->priv; unsigned long ioaddr = dev->base_addr; if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { unsigned int old_bank; /* duplex state has changed */ if (lp->mii.full_duplex) { lp->tcr_cur_mode |= TCR_SWFDUP; } else { lp->tcr_cur_mode &= ~TCR_SWFDUP; } old_bank = SMC_CURRENT_BANK(); SMC_SELECT_BANK(0); SMC_SET_TCR(lp->tcr_cur_mode); SMC_SELECT_BANK(old_bank); }}/*------------------------------------------------------------ . Configures the specified PHY through the MII management interface . using Autonegotiation. . Calls smc_phy_fixed() if the user has requested a certain config. . If RPC ANEG bit is set, the media selection is dependent purely on . the selection by the MII (either in the MII BMCR reg or the result . of autonegotiation.) If the RPC ANEG bit is cleared, the selection . is controlled by the RPC SPEED and RPC DPLX bits. .-------------------------------------------------------------*/static void smc_phy_configure(struct net_device* dev){ struct smc_local *lp = (struct smc_local *)dev->priv; unsigned long ioaddr = dev->base_addr; int phyaddr = lp->mii.phy_id; int my_phy_caps; // My PHY capabilities int my_ad_caps; // My Advertised capabilities int status; PRINTK3("%s:smc_program_phy()\n", dev->name); spin_lock_irq(&lp->lock); // We should not be called if phy_type is zero. if (lp->phy_type == 0) goto smc_phy_configure_exit; if (smc_phy_reset(dev, phyaddr)) { printk("%s: PHY reset timed out\n", dev->name); goto smc_phy_configure_exit; } // Enable PHY Interrupts (for register 18) // Interrupts listed here are disabled smc_phy_write(dev, phyaddr, PHY_MASK_REG, PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | PHY_INT_SPDDET | PHY_INT_DPLXDET); /* Configure the Receive/Phy Control register */ SMC_SELECT_BANK( 0 ); SMC_SET_RPC( lp->rpc_cur_mode ); // If the user requested no auto neg, then go set his request if (lp->mii.force_media) { smc_phy_fixed(dev); goto smc_phy_configure_exit; } // Copy our capabilities from MII_BMSR to MII_ADVERTISE my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { printk(KERN_INFO "Auto negotiation NOT supported\n"); smc_phy_fixed(dev); goto smc_phy_configure_exit; } my_ad_caps = ADVERTISE_CSMA; // I am CSMA capable if (my_phy_caps & BMSR_100BASE4) my_ad_caps |= ADVERTISE_100BASE4; if (my_phy_caps & BMSR_100FULL) my_ad_caps |= ADVERTISE_100FULL; if (my_phy_caps & BMSR_100HALF) my_ad_caps |= ADVERTISE_100HALF; if (my_phy_caps & BMSR_10FULL) my_ad_caps |= ADVERTISE_10FULL; if (my_phy_caps & BMSR_10HALF) my_ad_caps |= ADVERTISE_10HALF; // Disable capabilities not selected by our user if (lp->ctl_rspeed != 100) my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); if (!lp->ctl_rfduplx) my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); // Update our Auto-Neg Advertisement Register smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); lp->mii.advertising = my_ad_caps; // Read the register back. Without this, it appears that when // auto-negotiation is restarted, sometimes it isn't ready and // the link does not come up. status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); PRINTK2("%s: phy caps=%x\n", dev->name, my_phy_caps); PRINTK2("%s: phy advertised caps=%x\n", dev->name, my_ad_caps); // Restart auto-negotiation process in order to advertise my caps smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
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