piix.c

优龙2410linux2.6.8内核源代码

/*
 *  linux/drivers/ide/pci/piix.c	Version 0.44	March 20, 2003
 *
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <[e-mail]>
 *  Copyright (C) 2003 Red Hat Inc <[e-mail]>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  PIO mode setting function for Intel chipsets.  
 *  For use instead of BIOS settings.
 *
 * 40-41
 * 42-43
 * 
 *                 41
 *                 43
 *
 * | PIO 0       | c0 | 80 | 0 | 	piix_tune_drive(drive, 0);
 * | PIO 2 | SW2 | d0 | 90 | 4 | 	piix_tune_drive(drive, 2);
 * | PIO 3 | MW1 | e1 | a1 | 9 | 	piix_tune_drive(drive, 3);
 * | PIO 4 | MW2 | e3 | a3 | b | 	piix_tune_drive(drive, 4);
 * 
 * sitre = word40 & 0x4000; primary
 * sitre = word42 & 0x4000; secondary
 *
 * 44 8421|8421    hdd|hdb
 * 
 * 48 8421         hdd|hdc|hdb|hda udma enabled
 *
 *    0001         hda
 *    0010         hdb
 *    0100         hdc
 *    1000         hdd
 *
 * 4a 84|21        hdb|hda
 * 4b 84|21        hdd|hdc
 *
 *    ata-33/82371AB
 *    ata-33/82371EB
 *    ata-33/82801AB            ata-66/82801AA
 *    00|00 udma 0              00|00 reserved
 *    01|01 udma 1              01|01 udma 3
 *    10|10 udma 2              10|10 udma 4
 *    11|11 reserved            11|11 reserved
 *
 * 54 8421|8421    ata66 drive|ata66 enable
 *
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
 *
 * Documentation
 *	Publically available from Intel web site. Errata documentation
 * is also publically available. As an aide to anyone hacking on this
 * driver the list of errata that are relevant is below.going back to
 * PIIX4. Older device documentation is now a bit tricky to find.
 *
 * Errata of note:
 *
 * Unfixable
 *	PIIX4    errata #9	- Only on ultra obscure hw
 *	ICH3	 errata #13     - Not observed to affect real hw
 *				  by Intel
 *
 * Things we must deal with
 *	PIIX4	errata #10	- BM IDE hang with non UDMA
 *				  (must stop/start dma to recover)
 *	440MX   errata #15	- As PIIX4 errata #10
 *	PIIX4	errata #15	- Must not read control registers
 * 				  during a PIO transfer
 *	440MX   errata #13	- As PIIX4 errata #15
 *	ICH2	errata #21	- DMA mode 0 doesn't work right
 *	ICH0/1  errata #55	- As ICH2 errata #21
 *	ICH2	spec c #9	- Extra operations needed to handle
 *				  drive hotswap [NOT YET SUPPORTED]
 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
 *				  and must be dword aligned
 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
 *
 * Should have been BIOS fixed:
 *	450NX:	errata #19	- DMA hangs on old 450NX
 *	450NX:  errata #20	- DMA hangs on old 450NX
 *	450NX:  errata #25	- Corruption with DMA on old 450NX
 *	ICH3    errata #15      - IDE deadlock under high load
 *				  (BIOS must set dev 31 fn 0 bit 23)
 *	ICH3	errata #18	- Don't use native mode
 */

#include <linux/config.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

#include "piix.h"

static int no_piix_dma;
#if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>

static u8 piix_proc = 0;
#define PIIX_MAX_DEVS		5
static struct pci_dev *piix_devs[PIIX_MAX_DEVS];
static int n_piix_devs;

/**
 *	piix_get_info		-	fill in /proc for PIIX ide
 *	@buffer: buffer to fill
 *	@addr: address of user start in buffer
 *	@offset: offset into 'file'
 *	@count: buffer count
 *
 *	Walks the PIIX devices and outputs summary data on the tuning and
 *	anything else that will help with debugging
 */
 
static int piix_get_info (char *buffer, char **addr, off_t offset, int count)
{
	char *p = buffer;
	int i;

	for (i = 0; i < n_piix_devs; i++) {
		struct pci_dev *dev	= piix_devs[i];
		unsigned long bibma = pci_resource_start(dev, 4);
	        u16 reg40 = 0, psitre = 0, reg42 = 0, ssitre = 0;
		u8  c0 = 0, c1 = 0, reg54 = 0, reg55 = 0;
		u8  reg44 = 0, reg48 = 0, reg4a = 0, reg4b = 0;

		p += sprintf(p, "\nController: %d\n", i);
		p += sprintf(p, "\n                                Intel ");
		switch(dev->device) {
			case PCI_DEVICE_ID_INTEL_82801EB_1:
				p += sprintf(p, "PIIX4 SATA 150 ");
				break;
			case PCI_DEVICE_ID_INTEL_82801BA_8:
			case PCI_DEVICE_ID_INTEL_82801BA_9:
			case PCI_DEVICE_ID_INTEL_82801CA_10:
			case PCI_DEVICE_ID_INTEL_82801CA_11:
			case PCI_DEVICE_ID_INTEL_82801DB_10:
			case PCI_DEVICE_ID_INTEL_82801DB_11:
			case PCI_DEVICE_ID_INTEL_82801EB_11:
			case PCI_DEVICE_ID_INTEL_82801E_11:
			case PCI_DEVICE_ID_INTEL_ESB_2:
			case PCI_DEVICE_ID_INTEL_ICH6_19:
				p += sprintf(p, "PIIX4 Ultra 100 ");
				break;
			case PCI_DEVICE_ID_INTEL_82372FB_1:
			case PCI_DEVICE_ID_INTEL_82801AA_1:
				p += sprintf(p, "PIIX4 Ultra 66 ");
				break;
			case PCI_DEVICE_ID_INTEL_82451NX:
			case PCI_DEVICE_ID_INTEL_82801AB_1:
			case PCI_DEVICE_ID_INTEL_82443MX_1:
			case PCI_DEVICE_ID_INTEL_82371AB:
				p += sprintf(p, "PIIX4 Ultra 33 ");
				break;
			case PCI_DEVICE_ID_INTEL_82371SB_1:
				p += sprintf(p, "PIIX3 ");
				break;
			case PCI_DEVICE_ID_INTEL_82371MX:
				p += sprintf(p, "MPIIX ");
				break;
			case PCI_DEVICE_ID_INTEL_82371FB_1:
			case PCI_DEVICE_ID_INTEL_82371FB_0:
			default:
				p += sprintf(p, "PIIX ");
				break;
		}
		p += sprintf(p, "Chipset.\n");

		if (dev->device == PCI_DEVICE_ID_INTEL_82371MX)
			continue;

		pci_read_config_word(dev, 0x40, &reg40);
		pci_read_config_word(dev, 0x42, &reg42);
		pci_read_config_byte(dev, 0x44, &reg44);
		pci_read_config_byte(dev, 0x48, &reg48);
		pci_read_config_byte(dev, 0x4a, &reg4a);
		pci_read_config_byte(dev, 0x4b, &reg4b);
		pci_read_config_byte(dev, 0x54, &reg54);
		pci_read_config_byte(dev, 0x55, &reg55);

		psitre = (reg40 & 0x4000) ? 1 : 0;
		ssitre = (reg42 & 0x4000) ? 1 : 0;

		/*
		 * at that point bibma+0x2 et bibma+0xa are byte registers
		 * to investigate:
		 */
		c0 = inb(bibma + 0x02);
		c1 = inb(bibma + 0x0a);

		p += sprintf(p, "--------------- Primary Channel "
				"---------------- Secondary Channel "
				"-------------\n");
		p += sprintf(p, "                %sabled "
				"                        %sabled\n",
				(c0&0x80) ? "dis" : " en",
				(c1&0x80) ? "dis" : " en");
		p += sprintf(p, "--------------- drive0 --------- drive1 "
				"-------- drive0 ---------- drive1 ------\n");
		p += sprintf(p, "DMA enabled:    %s              %s "
				"            %s               %s\n",
				(c0&0x20) ? "yes" : "no ",
				(c0&0x40) ? "yes" : "no ",
				(c1&0x20) ? "yes" : "no ",
				(c1&0x40) ? "yes" : "no " );
		p += sprintf(p, "UDMA enabled:   %s              %s "
				"            %s               %s\n",
				(reg48&0x01) ? "yes" : "no ",
				(reg48&0x02) ? "yes" : "no ",
				(reg48&0x04) ? "yes" : "no ",
				(reg48&0x08) ? "yes" : "no " );
		p += sprintf(p, "UDMA enabled:   %s                %s "
				"              %s                 %s\n",
				((reg54&0x11) &&
				 (reg55&0x10) && (reg4a&0x01)) ? "5" :
				((reg54&0x11) && (reg4a&0x02)) ? "4" :
				((reg54&0x11) && (reg4a&0x01)) ? "3" :
				(reg4a&0x02) ? "2" :
				(reg4a&0x01) ? "1" :
				(reg4a&0x00) ? "0" : "X",
				((reg54&0x22) &&
				 (reg55&0x20) && (reg4a&0x10)) ? "5" :
				((reg54&0x22) && (reg4a&0x20)) ? "4" :
				((reg54&0x22) && (reg4a&0x10)) ? "3" :
				(reg4a&0x20) ? "2" :
				(reg4a&0x10) ? "1" :
				(reg4a&0x00) ? "0" : "X",
				((reg54&0x44) &&
				 (reg55&0x40) && (reg4b&0x03)) ? "5" :
				((reg54&0x44) && (reg4b&0x02)) ? "4" :
				((reg54&0x44) && (reg4b&0x01)) ? "3" :
				(reg4b&0x02) ? "2" :
				(reg4b&0x01) ? "1" :
				(reg4b&0x00) ? "0" : "X",
				((reg54&0x88) &&
				 (reg55&0x80) && (reg4b&0x30)) ? "5" :
				((reg54&0x88) && (reg4b&0x20)) ? "4" :
				((reg54&0x88) && (reg4b&0x10)) ? "3" :
				(reg4b&0x20) ? "2" :
				(reg4b&0x10) ? "1" :
				(reg4b&0x00) ? "0" : "X");

		p += sprintf(p, "UDMA\n");
		p += sprintf(p, "DMA\n");
		p += sprintf(p, "PIO\n");

		/*
		 * FIXME.... Add configuration junk data....blah blah......
		 */
	}
	return p-buffer;	 /* => must be less than 4k! */
}
#endif  /* defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS) */

/**
 *	piix_ratemask		-	compute rate mask for PIIX IDE
 *	@drive: IDE drive to compute for
 *
 *	Returns the available modes for the PIIX IDE controller.
 */
 
static u8 piix_ratemask (ide_drive_t *drive)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	u8 mode;

	switch(dev->device) {
		case PCI_DEVICE_ID_INTEL_82801EB_1:
			mode = 3;
			break;
		/* UDMA 100 capable */
		case PCI_DEVICE_ID_INTEL_82801BA_8:
		case PCI_DEVICE_ID_INTEL_82801BA_9:
		case PCI_DEVICE_ID_INTEL_82801CA_10:
		case PCI_DEVICE_ID_INTEL_82801CA_11:
		case PCI_DEVICE_ID_INTEL_82801E_11:
		case PCI_DEVICE_ID_INTEL_82801DB_10:
		case PCI_DEVICE_ID_INTEL_82801DB_11:
		case PCI_DEVICE_ID_INTEL_82801EB_11:
		case PCI_DEVICE_ID_INTEL_ESB_2:
		case PCI_DEVICE_ID_INTEL_ICH6_19:
			mode = 3;
			break;
		/* UDMA 66 capable */
		case PCI_DEVICE_ID_INTEL_82801AA_1:
		case PCI_DEVICE_ID_INTEL_82372FB_1:
			mode = 2;
			break;
		/* UDMA 33 capable */
		case PCI_DEVICE_ID_INTEL_82371AB:
		case PCI_DEVICE_ID_INTEL_82443MX_1:
		case PCI_DEVICE_ID_INTEL_82451NX:
		case PCI_DEVICE_ID_INTEL_82801AB_1:
			return 1;
		/* Non UDMA capable (MWDMA2) */
		case PCI_DEVICE_ID_INTEL_82371SB_1:
		case PCI_DEVICE_ID_INTEL_82371FB_1:
		case PCI_DEVICE_ID_INTEL_82371FB_0:
		case PCI_DEVICE_ID_INTEL_82371MX:
		default:
			return 0;
	}
	
	/*
	 *	If we are UDMA66 capable fall back to UDMA33 
	 *	if the drive cannot see an 80pin cable.
	 */
	if (!eighty_ninty_three(drive))
		mode = min(mode, (u8)1);
	return mode;
}

/**
 *	piix_dma_2_pio		-	return the PIO mode matching DMA
 *	@xfer_rate: transfer speed
 *
 *	Returns the nearest equivalent PIO timing for the PIO or DMA
 *	mode requested by the controller.
 */
 
static u8 piix_dma_2_pio (u8 xfer_rate) {
	switch(xfer_rate) {
		case XFER_UDMA_6:
		case XFER_UDMA_5:
		case XFER_UDMA_4:
		case XFER_UDMA_3:
		case XFER_UDMA_2:
		case XFER_UDMA_1:
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:
		case XFER_PIO_4:
			return 4;
		case XFER_MW_DMA_1:
		case XFER_PIO_3:
			return 3;
		case XFER_SW_DMA_2:
		case XFER_PIO_2:
			return 2;
		case XFER_MW_DMA_0:
		case XFER_SW_DMA_1:
		case XFER_SW_DMA_0:
		case XFER_PIO_1:
		case XFER_PIO_0:
		case XFER_PIO_SLOW:
		default:
			return 0;
	}
}

/**
 *	piix_tune_drive		-	tune a drive attached to a PIIX
 *	@drive: drive to tune
 *	@pio: desired PIO mode
 *
 *	Set the interface PIO mode based upon  the settings done by AMI BIOS
 *	(might be useful if drive is not registered in CMOS for any reason).
 */
static void piix_tune_drive (ide_drive_t *drive, u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	int is_slave		= (&hwif->drives[1] == drive);
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
				 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
	spin_lock_irqsave(&ide_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);
	if (is_slave) {
		master_data = master_data | 0x4000;
		if (pio > 1)
			/* enable PPE, IE and TIME */
			master_data = master_data | 0x0070;
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
		slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
	} else {
		master_data = master_data & 0xccf8;
		if (pio > 1)
			/* enable PPE, IE and TIME */
			master_data = master_data | 0x0007;
		master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&ide_lock, flags);
}