ibmphp_hpc.c

优龙2410linux2.6.8内核源代码

/*
 * IBM Hot Plug Controller Driver
 *
 * Written By: Jyoti Shah, IBM Corporation
 *
 * Copyright (C) 2001-2003 IBM Corp.
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Send feedback to <[e-mail]>
 *                  <[e-mail]>
 *
 */

#include <linux/wait.h>
#include <linux/time.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/smp_lock.h>
#include <linux/init.h>
#include "ibmphp.h"

static int to_debug = FALSE;
#define debug_polling(fmt, arg...)	do { if (to_debug) debug (fmt, arg); } while (0)

//----------------------------------------------------------------------------
// timeout values
//----------------------------------------------------------------------------
#define CMD_COMPLETE_TOUT_SEC	60	// give HPC 60 sec to finish cmd
#define HPC_CTLR_WORKING_TOUT	60	// give HPC 60 sec to finish cmd
#define HPC_GETACCESS_TIMEOUT	60	// seconds
#define POLL_INTERVAL_SEC	2	// poll HPC every 2 seconds
#define POLL_LATCH_CNT		5	// poll latch 5 times, then poll slots

//----------------------------------------------------------------------------
// Winnipeg Architected Register Offsets
//----------------------------------------------------------------------------
#define WPG_I2CMBUFL_OFFSET	0x08	// I2C Message Buffer Low
#define WPG_I2CMOSUP_OFFSET	0x10	// I2C Master Operation Setup Reg
#define WPG_I2CMCNTL_OFFSET	0x20	// I2C Master Control Register
#define WPG_I2CPARM_OFFSET	0x40	// I2C Parameter Register
#define WPG_I2CSTAT_OFFSET	0x70	// I2C Status Register

//----------------------------------------------------------------------------
// Winnipeg Store Type commands (Add this commands to the register offset)
//----------------------------------------------------------------------------
#define WPG_I2C_AND		0x1000	// I2C AND operation
#define WPG_I2C_OR		0x2000	// I2C OR operation

//----------------------------------------------------------------------------
// Command set for I2C Master Operation Setup Regisetr
//----------------------------------------------------------------------------
#define WPG_READATADDR_MASK	0x00010000	// read,bytes,I2C shifted,index
#define WPG_WRITEATADDR_MASK	0x40010000	// write,bytes,I2C shifted,index
#define WPG_READDIRECT_MASK	0x10010000
#define WPG_WRITEDIRECT_MASK	0x60010000


//----------------------------------------------------------------------------
// bit masks for I2C Master Control Register
//----------------------------------------------------------------------------
#define WPG_I2CMCNTL_STARTOP_MASK	0x00000002	// Start the Operation

//----------------------------------------------------------------------------
//
//----------------------------------------------------------------------------
#define WPG_I2C_IOREMAP_SIZE	0x2044	// size of linear address interval

//----------------------------------------------------------------------------
// command index
//----------------------------------------------------------------------------
#define WPG_1ST_SLOT_INDEX	0x01	// index - 1st slot for ctlr
#define WPG_CTLR_INDEX		0x0F	// index - ctlr
#define WPG_1ST_EXTSLOT_INDEX	0x10	// index - 1st ext slot for ctlr
#define WPG_1ST_BUS_INDEX	0x1F	// index - 1st bus for ctlr

//----------------------------------------------------------------------------
// macro utilities
//----------------------------------------------------------------------------
// if bits 20,22,25,26,27,29,30 are OFF return TRUE
#define HPC_I2CSTATUS_CHECK(s)	((u8)((s & 0x00000A76) ? FALSE : TRUE))

//----------------------------------------------------------------------------
// global variables
//----------------------------------------------------------------------------
static int ibmphp_shutdown;
static int tid_poll;
static struct semaphore sem_hpcaccess;	// lock access to HPC
static struct semaphore semOperations;	// lock all operations and
					// access to data structures
static struct semaphore sem_exit;	// make sure polling thread goes away
//----------------------------------------------------------------------------
// local function prototypes
//----------------------------------------------------------------------------
static u8 i2c_ctrl_read (struct controller *, void *, u8);
static u8 i2c_ctrl_write (struct controller *, void *, u8, u8);
static u8 hpc_writecmdtoindex (u8, u8);
static u8 hpc_readcmdtoindex (u8, u8);
static void get_hpc_access (void);
static void free_hpc_access (void);
static void poll_hpc (void);
static int process_changeinstatus (struct slot *, struct slot *);
static int process_changeinlatch (u8, u8, struct controller *);
static int hpc_poll_thread (void *);
static int hpc_wait_ctlr_notworking (int, struct controller *, void *, u8 *);
//----------------------------------------------------------------------------


/*----------------------------------------------------------------------
* Name:    ibmphp_hpc_initvars
*
* Action:  initialize semaphores and variables
*---------------------------------------------------------------------*/
void __init ibmphp_hpc_initvars (void)
{
	debug ("%s - Entry\n", __FUNCTION__);

	init_MUTEX (&sem_hpcaccess);
	init_MUTEX (&semOperations);
	init_MUTEX_LOCKED (&sem_exit);
	to_debug = FALSE;
	ibmphp_shutdown = FALSE;
	tid_poll = 0;

	debug ("%s - Exit\n", __FUNCTION__);
}

/*----------------------------------------------------------------------
* Name:    i2c_ctrl_read
*
* Action:  read from HPC over I2C
*
*---------------------------------------------------------------------*/
static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void *WPGBbar, u8 index)
{
	u8 status;
	int i;
	void *wpg_addr;		// base addr + offset
	unsigned long wpg_data;	// data to/from WPG LOHI format
	unsigned long ultemp;
	unsigned long data;	// actual data HILO format

	debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __FUNCTION__, WPGBbar, index);

	//--------------------------------------------------------------------
	// READ - step 1
	// read at address, byte length, I2C address (shifted), index
	// or read direct, byte length, index
	if (ctlr_ptr->ctlr_type == 0x02) {
		data = WPG_READATADDR_MASK;
		// fill in I2C address
		ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
		ultemp = ultemp >> 1;
		data |= (ultemp << 8);

		// fill in index
		data |= (unsigned long)index;
	} else if (ctlr_ptr->ctlr_type == 0x04) {
		data = WPG_READDIRECT_MASK;

		// fill in index
		ultemp = (unsigned long)index;
		ultemp = ultemp << 8;
		data |= ultemp;
	} else {
		err ("this controller type is not supported \n");
		return HPC_ERROR;
	}

	wpg_data = swab32 (data);	// swap data before writing
	wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
	writel (wpg_data, wpg_addr);

	//--------------------------------------------------------------------
	// READ - step 2 : clear the message buffer
	data = 0x00000000;
	wpg_data = swab32 (data);
	wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
	writel (wpg_data, wpg_addr);

	//--------------------------------------------------------------------
	// READ - step 3 : issue start operation, I2C master control bit 30:ON
	//                 2020 : [20] OR operation at [20] offset 0x20
	data = WPG_I2CMCNTL_STARTOP_MASK;
	wpg_data = swab32 (data);
	wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
	writel (wpg_data, wpg_addr);

	//--------------------------------------------------------------------
	// READ - step 4 : wait until start operation bit clears
	i = CMD_COMPLETE_TOUT_SEC;
	while (i) {
		long_delay (1 * HZ / 100);
		wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
		wpg_data = readl (wpg_addr);
		data = swab32 (wpg_data);
		if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
			break;
		i--;
	}
	if (i == 0) {
		debug ("%s - Error : WPG timeout\n", __FUNCTION__);
		return HPC_ERROR;
	}
	//--------------------------------------------------------------------
	// READ - step 5 : read I2C status register
	i = CMD_COMPLETE_TOUT_SEC;
	while (i) {
		long_delay (1 * HZ / 100);
		wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
		wpg_data = readl (wpg_addr);
		data = swab32 (wpg_data);
		if (HPC_I2CSTATUS_CHECK (data))
			break;
		i--;
	}
	if (i == 0) {
		debug ("ctrl_read - Exit Error:I2C timeout\n");
		return HPC_ERROR;
	}

	//--------------------------------------------------------------------
	// READ - step 6 : get DATA
	wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
	wpg_data = readl (wpg_addr);
	data = swab32 (wpg_data);

	status = (u8) data;

	debug_polling ("%s - Exit index[%x] status[%x]\n", __FUNCTION__, index, status);

	return (status);
}

/*----------------------------------------------------------------------
* Name:    i2c_ctrl_write
*
* Action:  write to HPC over I2C
*
* Return   0 or error codes
*---------------------------------------------------------------------*/
static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void *WPGBbar, u8 index, u8 cmd)
{
	u8 rc;
	void *wpg_addr;		// base addr + offset
	unsigned long wpg_data;	// data to/from WPG LOHI format 
	unsigned long ultemp;
	unsigned long data;	// actual data HILO format
	int i;

	debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __FUNCTION__, WPGBbar, index, cmd);

	rc = 0;
	//--------------------------------------------------------------------
	// WRITE - step 1
	// write at address, byte length, I2C address (shifted), index
	// or write direct, byte length, index
	data = 0x00000000;

	if (ctlr_ptr->ctlr_type == 0x02) {
		data = WPG_WRITEATADDR_MASK;
		// fill in I2C address
		ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
		ultemp = ultemp >> 1;
		data |= (ultemp << 8);

		// fill in index
		data |= (unsigned long)index;
	} else if (ctlr_ptr->ctlr_type == 0x04) {
		data = WPG_WRITEDIRECT_MASK;

		// fill in index
		ultemp = (unsigned long)index;
		ultemp = ultemp << 8;
		data |= ultemp;
	} else {
		err ("this controller type is not supported \n");
		return HPC_ERROR;
	}

	wpg_data = swab32 (data);	// swap data before writing
	wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
	writel (wpg_data, wpg_addr);

	//--------------------------------------------------------------------
	// WRITE - step 2 : clear the message buffer
	data = 0x00000000 | (unsigned long)cmd;
	wpg_data = swab32 (data);
	wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
	writel (wpg_data, wpg_addr);

	//--------------------------------------------------------------------
	// WRITE - step 3 : issue start operation,I2C master control bit 30:ON
	//                 2020 : [20] OR operation at [20] offset 0x20
	data = WPG_I2CMCNTL_STARTOP_MASK;
	wpg_data = swab32 (data);
	wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
	writel (wpg_data, wpg_addr);

	//--------------------------------------------------------------------
	// WRITE - step 4 : wait until start operation bit clears
	i = CMD_COMPLETE_TOUT_SEC;
	while (i) {
		long_delay (1 * HZ / 100);
		wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
		wpg_data = readl (wpg_addr);
		data = swab32 (wpg_data);
		if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
			break;
		i--;
	}
	if (i == 0) {
		debug ("%s - Exit Error:WPG timeout\n", __FUNCTION__);
		rc = HPC_ERROR;
	}

	//--------------------------------------------------------------------
	// WRITE - step 5 : read I2C status register
	i = CMD_COMPLETE_TOUT_SEC;
	while (i) {
		long_delay (1 * HZ / 100);
		wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
		wpg_data = readl (wpg_addr);
		data = swab32 (wpg_data);
		if (HPC_I2CSTATUS_CHECK (data))
			break;
		i--;
	}
	if (i == 0) {
		debug ("ctrl_read - Error : I2C timeout\n");
		rc = HPC_ERROR;
	}

	debug_polling ("%s Exit rc[%x]\n", __FUNCTION__, rc);
	return (rc);
}

//------------------------------------------------------------
//  Read from ISA type HPC 
//------------------------------------------------------------
static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset)
{
	u16 start_address;
	u16 end_address;
	u8 data;

	start_address = ctlr_ptr->u.isa_ctlr.io_start;
	end_address = ctlr_ptr->u.isa_ctlr.io_end;
	data = inb (start_address + offset);
	return data;
}

//--------------------------------------------------------------
// Write to ISA type HPC
//--------------------------------------------------------------
static void isa_ctrl_write (struct controller *ctlr_ptr, u8 offset, u8 data)
{
	u16 start_address;
	u16 port_address;
	
	start_address = ctlr_ptr->u.isa_ctlr.io_start;
	port_address = start_address + (u16) offset;
	outb (data, port_address);
}

static u8 pci_ctrl_read (struct controller *ctrl, u8 offset)
{
	u8 data = 0x00;
	debug ("inside pci_ctrl_read\n");
	if (ctrl->ctrl_dev)
		pci_read_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data);
	return data;
}