k2.c

优龙2410linux2.6.8内核源代码

				   K2_PCI64_CONFIG_ADDR, K2_PCI64_CONFIG_DATA);

		/* Initialize PCI64 bus registers */
		early_write_config_byte(hose_b,
					0,
					PCI_DEVFN(0, 0),
					CPC710_SUB_BUS_NUMBER, 0xff);

		early_write_config_byte(hose_b,
					0,
					PCI_DEVFN(0, 0),
					CPC710_BUS_NUMBER, hose_b->first_busno);

		hose_b->last_busno = pciauto_bus_scan(hose_b,
						      hose_b->first_busno);

		/* Write out correct max subordinate bus number for hose B */
		early_write_config_byte(hose_b,
					hose_b->first_busno,
					PCI_DEVFN(0, 0),
					CPC710_SUB_BUS_NUMBER,
					hose_b->last_busno);

		/* Configure PCI64 PSBAR */
		early_write_config_dword(hose_b,
					 hose_b->first_busno,
					 PCI_DEVFN(0, 0),
					 PCI_BASE_ADDRESS_0,
					 K2_PCI64_SYS_MEM_BASE);
	}

	/* Configure i8259 level/edge settings */
	outb(0x62, 0x4d0);
	outb(0xde, 0x4d1);

#ifdef CONFIG_CPC710_DATA_GATHERING
	{
		unsigned int tmp;
		tmp = __raw_readl(ABCNTL);
		/* Enable data gathering on both PCI interfaces */
		__raw_writel(tmp | 0x05000000, ABCNTL);
	}
#endif

	ppc_md.pcibios_fixup = k2_pcibios_fixup;
	ppc_md.pcibios_fixup_resources = k2_pcibios_fixup_resources;
	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = k2_map_irq;
}

static int k2_get_bus_speed(void)
{
	int bus_speed;
	unsigned char board_id;

	board_id = *(unsigned char *)K2_BOARD_ID_REG;

	switch (K2_BUS_SPD(board_id)) {

	case 0:
	default:
		bus_speed = 100000000;
		break;

	case 1:
		bus_speed = 83333333;
		break;

	case 2:
		bus_speed = 75000000;
		break;

	case 3:
		bus_speed = 66666666;
		break;
	}
	return bus_speed;
}

static int k2_get_cpu_speed(void)
{
	unsigned long hid1;
	int cpu_speed;

	hid1 = mfspr(HID1) >> 28;

	if ((mfspr(PVR) >> 16) == 8)
		hid1 = cpu_7xx[hid1];
	else
		hid1 = cpu_6xx[hid1];

	cpu_speed = k2_get_bus_speed() * hid1 / 2;
	return cpu_speed;
}

static void __init k2_calibrate_decr(void)
{
	int freq, divisor = 4;

	/* determine processor bus speed */
	freq = k2_get_bus_speed();
	tb_ticks_per_jiffy = freq / HZ / divisor;
	tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
}

static int k2_show_cpuinfo(struct seq_file *m)
{
	unsigned char k2_geo_bits, k2_system_slot;

	seq_printf(m, "vendor\t\t: SBS\n");
	seq_printf(m, "machine\t\t: K2\n");
	seq_printf(m, "cpu speed\t: %dMhz\n", k2_get_cpu_speed() / 1000000);
	seq_printf(m, "bus speed\t: %dMhz\n", k2_get_bus_speed() / 1000000);
	seq_printf(m, "memory type\t: SDRAM\n");

	k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK;
	k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK);
	seq_printf(m, "backplane\t: %s slot board",
		   k2_system_slot ? "System" : "Non system");
	seq_printf(m, "with geographical address %x\n", k2_geo_bits);

	return 0;
}

TODC_ALLOC();

static void __init k2_setup_arch(void)
{
	unsigned int cpu;

	/* Setup TODC access */
	TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
		  ioremap(K2_RTC_BASE_ADDRESS, K2_RTC_SIZE), 8);

	/* init to some ~sane value until calibrate_delay() runs */
	loops_per_jiffy = 50000000 / HZ;

	/* make FLASH transactions higher priority than PCI to avoid deadlock */
	__raw_writel(__raw_readl(SIOC1) | 0x80000000, SIOC1);

	/* Set hardware to access FLASH page 2 */
	__raw_writel(1 << 29, GPOUT);

	/* Setup PCI host bridges */
	k2_setup_hoses();

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
#ifdef CONFIG_ROOT_NFS
		ROOT_DEV = Root_NFS;
#else
		ROOT_DEV = Root_HDC1;
#endif

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	/* Identify the system */
	printk(KERN_INFO "System Identification: SBS K2 - PowerPC 750 @ "
			"%d Mhz\n", k2_get_cpu_speed() / 1000000);
	printk(KERN_INFO "Port by MontaVista Software, Inc. "
			"([e-mail])\n");

	/* Identify the CPU manufacturer */
	cpu = PVR_REV(mfspr(PVR));
	printk(KERN_INFO "CPU manufacturer: %s [rev=%04x]\n",
			(cpu & (1 << 15)) ? "IBM" : "Motorola", cpu);
}

static void k2_restart(char *cmd)
{
	local_irq_disable();

	/* Flip FLASH back to page 1 to access firmware image */
	__raw_writel(0, GPOUT);

	/* SRR0 has system reset vector, SRR1 has default MSR value */
	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
	mtspr(SRR0, 0xfff00100);
	mtspr(SRR1, 0);
	__asm__ __volatile__("rfi\n\t");

	/* not reached */
	for (;;) ;
}

static void k2_power_off(void)
{
	for (;;) ;
}

static void k2_halt(void)
{
	k2_restart(NULL);
}

/*
 * Set BAT 3 to map PCI32 I/O space.
 */
static __inline__ void k2_set_bat(void)
{
	/* wait for all outstanding memory accesses to complete */
	mb();

	/* setup DBATs */
	mtspr(DBAT2U, 0x80001ffe);
	mtspr(DBAT2L, 0x8000002a);
	mtspr(DBAT3U, 0xf0001ffe);
	mtspr(DBAT3L, 0xf000002a);

	/* wait for updates */
	mb();
}

static unsigned long __init k2_find_end_of_memory(void)
{
	unsigned long total;
	unsigned char msize = 7;	/* Default to 128MB */

	msize = K2_MEM_SIZE(readb(K2_MSIZ_GEO_REG));

	switch (msize) {
	case 2:
		/*
		 * This will break without a lowered
		 * KERNELBASE or CONFIG_HIGHMEM on.
		 * It seems non 1GB builds exist yet,
		 * though.
		 */
		total = K2_MEM_SIZE_1GB;
		break;
	case 3:
	case 4:
		total = K2_MEM_SIZE_512MB;
		break;
	case 5:
	case 6:
		total = K2_MEM_SIZE_256MB;
		break;
	case 7:
		total = K2_MEM_SIZE_128MB;
		break;
	default:
		printk
		    ("K2: Invalid memory size detected, defaulting to 128MB\n");
		total = K2_MEM_SIZE_128MB;
		break;
	}
	return total;
}

static void __init k2_map_io(void)
{
	io_block_mapping(K2_PCI32_IO_BASE,
			 K2_PCI32_IO_BASE, 0x00200000, _PAGE_IO);
	io_block_mapping(0xff000000, 0xff000000, 0x01000000, _PAGE_IO);
}

static void __init k2_init_irq(void)
{
	int i;

	for (i = 0; i < 16; i++)
		irq_desc[i].handler = &i8259_pic;

	i8259_init(0);
}

void __init platform_init(unsigned long r3, unsigned long r4,
			  unsigned long r5, unsigned long r6, unsigned long r7)
{
	parse_bootinfo((struct bi_record *)(r3 + KERNELBASE));

	k2_set_bat();

	isa_io_base = K2_ISA_IO_BASE;
	isa_mem_base = K2_ISA_MEM_BASE;
	pci_dram_offset = K2_PCI32_SYS_MEM_BASE;

	ppc_md.setup_arch = k2_setup_arch;
	ppc_md.show_cpuinfo = k2_show_cpuinfo;
	ppc_md.init_IRQ = k2_init_irq;
	ppc_md.get_irq = i8259_irq;

	ppc_md.find_end_of_memory = k2_find_end_of_memory;
	ppc_md.setup_io_mappings = k2_map_io;

	ppc_md.restart = k2_restart;
	ppc_md.power_off = k2_power_off;
	ppc_md.halt = k2_halt;

	ppc_md.time_init = todc_time_init;
	ppc_md.set_rtc_time = todc_set_rtc_time;
	ppc_md.get_rtc_time = todc_get_rtc_time;
	ppc_md.calibrate_decr = k2_calibrate_decr;

	ppc_md.nvram_read_val = todc_direct_read_val;
	ppc_md.nvram_write_val = todc_direct_write_val;

#ifdef CONFIG_SERIAL_TEXT_DEBUG
	ppc_md.progress = gen550_progress;
#endif
}