pmac_smp.c

来自「优龙2410linux2.6.8内核源代码」· C语言 代码 · 共 634 行 · 第 1/2 页

	if (psurge_type != PSURGE_DUAL) {
		psurge_quad_init();
		/* All released cards using this HW design have 4 CPUs */
		ncpus = 4;
	} else {
		iounmap((void *) quad_base);
		if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
			/* not a dual-cpu card */
			iounmap((void *) hhead_base);
			psurge_type = PSURGE_NONE;
			return 1;
		}
		ncpus = 2;
	}

	psurge_start = ioremap(PSURGE_START, 4);
	psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);

	/* this is not actually strictly necessary -- paulus. */
	for (i = 1; i < ncpus; ++i)
		smp_hw_index[i] = i;

	if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);

	return ncpus;
}

static void __init smp_psurge_kick_cpu(int nr)
{
	void (*start)(void) = __secondary_start_psurge;
	unsigned long a;

	/* may need to flush here if secondary bats aren't setup */
	for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
		asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
	asm volatile("sync");

	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);

	/* setup entry point of secondary processor */
	switch (nr) {
	case 2:
		start = __secondary_start_psurge2;
		break;
	case 3:
		start = __secondary_start_psurge3;
		break;
	}

	out_be32(psurge_start, __pa(start));
	mb();

	psurge_set_ipi(nr);
	udelay(10);
	psurge_clr_ipi(nr);

	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
}

/*
 * With the dual-cpu powersurge board, the decrementers and timebases
 * of both cpus are frozen after the secondary cpu is started up,
 * until we give the secondary cpu another interrupt.  This routine
 * uses this to get the timebases synchronized.
 *  -- paulus.
 */
static void __init psurge_dual_sync_tb(int cpu_nr)
{
	int t;

	set_dec(tb_ticks_per_jiffy);
	set_tb(0, 0);
	last_jiffy_stamp(cpu_nr) = 0;

	if (cpu_nr > 0) {
		mb();
		sec_tb_reset = 1;
		return;
	}

	/* wait for the secondary to have reset its TB before proceeding */
	for (t = 10000000; t > 0 && !sec_tb_reset; --t)
		;

	/* now interrupt the secondary, starting both TBs */
	psurge_set_ipi(1);

	smp_tb_synchronized = 1;
}

static void __init smp_psurge_setup_cpu(int cpu_nr)
{

	if (cpu_nr == 0) {
		/* If we failed to start the second CPU, we should still
		 * send it an IPI to start the timebase & DEC or we might
		 * have them stuck.
		 */
		if (num_online_cpus() < 2) {
			if (psurge_type == PSURGE_DUAL)
				psurge_set_ipi(1);
			return;
		}
		/* reset the entry point so if we get another intr we won't
		 * try to startup again */
		out_be32(psurge_start, 0x100);
		if (request_irq(30, psurge_primary_intr, SA_INTERRUPT, "primary IPI", NULL))
			printk(KERN_ERR "Couldn't get primary IPI interrupt");
	}

	if (psurge_type == PSURGE_DUAL)
		psurge_dual_sync_tb(cpu_nr);
}

void __init smp_psurge_take_timebase(void)
{
	/* Dummy implementation */
}

void __init smp_psurge_give_timebase(void)
{
	/* Dummy implementation */
}

static int __init smp_core99_probe(void)
{
#ifdef CONFIG_6xx
	extern int powersave_nap;
#endif
	struct device_node *cpus, *firstcpu;
	int i, ncpus = 0, boot_cpu = -1;
	u32 *tbprop;

	if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
	cpus = firstcpu = find_type_devices("cpu");
	while(cpus != NULL) {
		u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);
		char *stateprop = (char *)get_property(cpus, "state", NULL);
		if (regprop != NULL && stateprop != NULL &&
		    !strncmp(stateprop, "running", 7))
			boot_cpu = *regprop;
		++ncpus;
		cpus = cpus->next;
	}
	if (boot_cpu == -1)
		printk(KERN_WARNING "Couldn't detect boot CPU !\n");
	if (boot_cpu != 0)
		printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);

	if (machine_is_compatible("MacRISC4")) {
		extern struct smp_ops_t core99_smp_ops;

		core99_smp_ops.take_timebase = smp_generic_take_timebase;
		core99_smp_ops.give_timebase = smp_generic_give_timebase;
	} else {
		if (firstcpu != NULL)
			tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);
		if (tbprop)
			core99_tb_gpio = *tbprop;
		else
			core99_tb_gpio = KL_GPIO_TB_ENABLE;
	}

	if (ncpus > 1) {
		openpic_request_IPIs();
		for (i = 1; i < ncpus; ++i)
			smp_hw_index[i] = i;
#ifdef CONFIG_6xx
		powersave_nap = 0;
#endif
		core99_init_caches(0);
	}

	return ncpus;
}

static void __init smp_core99_kick_cpu(int nr)
{
	unsigned long save_vector, new_vector;
	unsigned long flags;

	volatile unsigned long *vector
		 = ((volatile unsigned long *)(KERNELBASE+0x100));
	if (nr < 1 || nr > 3)
		return;
	if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);

	local_irq_save(flags);
	local_irq_disable();

	/* Save reset vector */
	save_vector = *vector;

	/* Setup fake reset vector that does	
	 *   b __secondary_start_psurge - KERNELBASE
	 */
	switch(nr) {
		case 1:
			new_vector = (unsigned long)__secondary_start_psurge;
			break;
		case 2:
			new_vector = (unsigned long)__secondary_start_psurge2;
			break;
		case 3:
			new_vector = (unsigned long)__secondary_start_psurge3;
			break;
	}
	*vector = 0x48000002 + new_vector - KERNELBASE;

	/* flush data cache and inval instruction cache */
	flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);

	/* Put some life in our friend */
	pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);

	/* FIXME: We wait a bit for the CPU to take the exception, I should
	 * instead wait for the entry code to set something for me. Well,
	 * ideally, all that crap will be done in prom.c and the CPU left
	 * in a RAM-based wait loop like CHRP.
	 */
	mdelay(1);

	/* Restore our exception vector */
	*vector = save_vector;
	flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);

	local_irq_restore(flags);
	if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
}

static void __init smp_core99_setup_cpu(int cpu_nr)
{
	/* Setup L2/L3 */
	if (cpu_nr != 0)
		core99_init_caches(cpu_nr);

	/* Setup openpic */
	do_openpic_setup_cpu();

	if (cpu_nr == 0) {
#ifdef CONFIG_POWER4
		extern void g5_phy_disable_cpu1(void);

		/* If we didn't start the second CPU, we must take
		 * it off the bus
		 */
		if (machine_is_compatible("MacRISC4") &&
		    num_online_cpus() < 2)		
			g5_phy_disable_cpu1();
#endif /* CONFIG_POWER4 */
		if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
	}
}

void __init smp_core99_take_timebase(void)
{
	/* Secondary processor "takes" the timebase by freezing
	 * it, resetting its local TB and telling CPU 0 to go on
	 */
	pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
	pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
	mb();

	set_dec(tb_ticks_per_jiffy);
	set_tb(0, 0);
	last_jiffy_stamp(smp_processor_id()) = 0;

	mb();
       	sec_tb_reset = 1;
}

void __init smp_core99_give_timebase(void)
{
	unsigned int t;

	/* Primary processor waits for secondary to have frozen
	 * the timebase, resets local TB, and kick timebase again
	 */
	/* wait for the secondary to have reset its TB before proceeding */
	for (t = 1000; t > 0 && !sec_tb_reset; --t)
		udelay(1000);
	if (t == 0)
		printk(KERN_WARNING "Timeout waiting sync on second CPU\n");

       	set_dec(tb_ticks_per_jiffy);
	set_tb(0, 0);
	last_jiffy_stamp(smp_processor_id()) = 0;
	mb();

	/* Now, restart the timebase by leaving the GPIO to an open collector */
       	pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
        pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);

	smp_tb_synchronized = 1;
}


/* PowerSurge-style Macs */
struct smp_ops_t psurge_smp_ops __pmacdata = {
	.message_pass	= smp_psurge_message_pass,
	.probe		= smp_psurge_probe,
	.kick_cpu	= smp_psurge_kick_cpu,
	.setup_cpu	= smp_psurge_setup_cpu,
	.give_timebase	= smp_psurge_give_timebase,
	.take_timebase	= smp_psurge_take_timebase,
};

/* Core99 Macs (dual G4s) */
struct smp_ops_t core99_smp_ops __pmacdata = {
	.message_pass	= smp_openpic_message_pass,
	.probe		= smp_core99_probe,
	.kick_cpu	= smp_core99_kick_cpu,
	.setup_cpu	= smp_core99_setup_cpu,
	.give_timebase	= smp_core99_give_timebase,
	.take_timebase	= smp_core99_take_timebase,
};