ide.c

优龙2410linux2.6.8内核源代码

        /* initiate a multi word read */

        *R_ATA_TRANSFER_CNT = wcount << 1;

        *R_ATA_CTRL_DATA = data_reg |
                IO_STATE(R_ATA_CTRL_DATA, rw,       read) |
                IO_STATE(R_ATA_CTRL_DATA, src_dst,  register) |
                IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
                IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
                IO_STATE(R_ATA_CTRL_DATA, dma_size, word);

        /* svinto has a latency until the busy bit actually is set */

        nop(); nop();
        nop(); nop();
        nop(); nop();
        nop(); nop();
        nop(); nop();

        /* unit should be busy during multi transfer */
        while((status = *R_ATA_STATUS_DATA) & IO_MASK(R_ATA_STATUS_DATA, busy)) {
                while(!(status & IO_MASK(R_ATA_STATUS_DATA, dav)))
                        status = *R_ATA_STATUS_DATA;
                *ptr++ = (unsigned short)(status & 0xffff);
        }
#endif
}

static void
e100_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
{
	ide_ioreg_t data_reg = IDE_DATA_REG;

	D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
		 data_reg, buffer, bytecount));

	if(bytecount & 1) {
		printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
		bytecount++;
	}

	/* make sure the DMA channel is available */
	RESET_DMA(ATA_TX_DMA_NBR);
	WAIT_DMA(ATA_TX_DMA_NBR);

	/* setup DMA descriptor */

	mydescr.sw_len = bytecount;
	mydescr.ctrl   = d_eol;
	mydescr.buf    = virt_to_phys(buffer);

	/* start the dma channel */

	*R_DMA_CH2_FIRST = virt_to_phys(&mydescr);
	*R_DMA_CH2_CMD   = IO_STATE(R_DMA_CH2_CMD, cmd, start);

	/* initiate a multi word dma write using PIO handshaking */

	*R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);

	*R_ATA_CTRL_DATA = data_reg |
		IO_STATE(R_ATA_CTRL_DATA, rw,       write) |
		IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma) |
		IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
		IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
		IO_STATE(R_ATA_CTRL_DATA, dma_size, word);

	/* wait for completion */

	LED_DISK_WRITE(1);
	WAIT_DMA(ATA_TX_DMA_NBR);
	LED_DISK_WRITE(0);

#if 0
        /* old polled write code - see comment in input_bytes */

	/* wait for busy flag */
        while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));

        /* initiate a multi word write */

        *R_ATA_TRANSFER_CNT = bytecount >> 1;

        ctrl = data_reg |
                IO_STATE(R_ATA_CTRL_DATA, rw,       write) |
                IO_STATE(R_ATA_CTRL_DATA, src_dst,  register) |
                IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
                IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
                IO_STATE(R_ATA_CTRL_DATA, dma_size, word);

        LED_DISK_WRITE(1);

        /* Etrax will set busy = 1 until the multi pio transfer has finished
         * and tr_rdy = 1 after each successful word transfer.
         * When the last byte has been transferred Etrax will first set tr_tdy = 1
         * and then busy = 0 (not in the same cycle). If we read busy before it
         * has been set to 0 we will think that we should transfer more bytes
         * and then tr_rdy would be 0 forever. This is solved by checking busy
         * in the inner loop.
         */

        do {
                *R_ATA_CTRL_DATA = ctrl | *ptr++;
                while(!(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy)) &&
                      (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)));
        } while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));

        LED_DISK_WRITE(0);
#endif

}

/*
 * This is used for most PIO data transfers *from* the IDE interface
 */
static void
e100_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
{
	e100_atapi_input_bytes(drive, buffer, wcount << 2);
}

/*
 * This is used for most PIO data transfers *to* the IDE interface
 */
static void
e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
{
	e100_atapi_output_bytes(drive, buffer, wcount << 2);
}

/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS];
static unsigned int ata_tot_size;

/*
 * e100_ide_build_dmatable() prepares a dma request.
 * Returns 0 if all went okay, returns 1 otherwise.
 */
static int e100_ide_build_dmatable (ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct scatterlist* sg;
	struct request *rq  = HWGROUP(drive)->rq;
	unsigned long size, addr;
	unsigned int count = 0;
	int i = 0;

	sg = hwif->sg_table;

	ata_tot_size = 0;

	if (HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE) {
		u8 *virt_addr = rq->buffer;
		int sector_count = rq->nr_sectors;
		memset(&sg[0], 0, sizeof(*sg));
		sg[0].page = virt_to_page(virt_addr);
		sg[0].offset = offset_in_page(virt_addr);
		sg[0].length =  sector_count  * SECTOR_SIZE;
		hwif->sg_nents = i = 1;
	}
	else
	{
		hwif->sg_nents = i = blk_rq_map_sg(drive->queue, rq, hwif->sg_table);
	}


	while(i) {
		/*
		 * Determine addr and size of next buffer area.  We assume that
		 * individual virtual buffers are always composed linearly in
		 * physical memory.  For example, we assume that any 8kB buffer
		 * is always composed of two adjacent physical 4kB pages rather
		 * than two possibly non-adjacent physical 4kB pages.
		 */
		/* group sequential buffers into one large buffer */
		addr = page_to_phys(sg->page) + sg->offset;
		size = sg_dma_len(sg);
		while (sg++, --i) {
			if ((addr + size) != page_to_phys(sg->page) + sg->offset)
				break;
			size += sg_dma_len(sg);
		}

		/* did we run out of descriptors? */

		if(count >= MAX_DMA_DESCRS) {
			printk("%s: too few DMA descriptors\n", drive->name);
			return 1;
		}

		/* however, this case is more difficult - R_ATA_TRANSFER_CNT cannot be more
		   than 65536 words per transfer, so in that case we need to either
		   1) use a DMA interrupt to re-trigger R_ATA_TRANSFER_CNT and continue with
		      the descriptors, or
		   2) simply do the request here, and get dma_intr to only ide_end_request on
		      those blocks that were actually set-up for transfer.
		*/

		if(ata_tot_size + size > 131072) {
			printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
			return 1;
		}

		/* If size > 65536 it has to be splitted into new descriptors. Since we don't handle
                   size > 131072 only one split is necessary */

		if(size > 65536) {
 		        /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
                        ata_descrs[count].sw_len = 0;  /* 0 means 65536, this is a 16-bit field */
                        ata_descrs[count].ctrl = 0;
                        ata_descrs[count].buf = addr;
                        ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
                        count++;
                        ata_tot_size += 65536;
                        /* size and addr should refere to not handled data */
                        size -= 65536;
                        addr += 65536;
                }
		/* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
                if(size == 65536) {
			ata_descrs[count].sw_len = 0;  /* 0 means 65536, this is a 16-bit field */
                } else {
			ata_descrs[count].sw_len = size;
                }
		ata_descrs[count].ctrl = 0;
		ata_descrs[count].buf = addr;
		ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
		count++;
		ata_tot_size += size;
	}

	if (count) {
		/* set the end-of-list flag on the last descriptor */
		ata_descrs[count - 1].ctrl |= d_eol;
		/* return and say all is ok */
		return 0;
	}

	printk("%s: empty DMA table?\n", drive->name);
	return 1;	/* let the PIO routines handle this weirdness */
}

static int config_drive_for_dma (ide_drive_t *drive)
{
        const char **list;
        struct hd_driveid *id = drive->id;

        if (id && (id->capability & 1)) {
                /* Enable DMA on any drive that supports mword2 DMA */
                if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
                        drive->using_dma = 1;
                        return 0;               /* DMA enabled */
                }

                /* Consult the list of known "good" drives */
                list = good_dma_drives;
                while (*list) {
                        if (!strcmp(*list++,id->model)) {
                                drive->using_dma = 1;
                                return 0;       /* DMA enabled */
                        }
                }
        }
        return 1;       /* DMA not enabled */
}

/*
 * etrax_dma_intr() is the handler for disk read/write DMA interrupts
 */
static ide_startstop_t etrax_dma_intr (ide_drive_t *drive)
{
	int i, dma_stat;
	byte stat;

	LED_DISK_READ(0);
	LED_DISK_WRITE(0);

	dma_stat = HWIF(drive)->ide_dma_end(drive);
	stat = HWIF(drive)->INB(IDE_STATUS_REG);		/* get drive status */
	if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
		if (!dma_stat) {
			struct request *rq;
			rq = HWGROUP(drive)->rq;
			for (i = rq->nr_sectors; i > 0;) {
				i -= rq->current_nr_sectors;
				DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
			}
			return ide_stopped;
		}
		printk("%s: bad DMA status\n", drive->name);
	}
	return DRIVER(drive)->error(drive, "dma_intr", stat);
}

/*
 * Functions below initiates/aborts DMA read/write operations on a drive.
 *
 * The caller is assumed to have selected the drive and programmed the drive's
 * sector address using CHS or LBA.  All that remains is to prepare for DMA
 * and then issue the actual read/write DMA/PIO command to the drive.
 *
 * For ATAPI devices, we just prepare for DMA and return. The caller should
 * then issue the packet command to the drive and call us again with
 * ide_dma_begin afterwards.
 *
 * Returns 0 if all went well.
 * Returns 1 if DMA read/write could not be started, in which case
 * the caller should revert to PIO for the current request.
 */

static int e100_dma_check(ide_drive_t *drive)
{
	return config_drive_for_dma (drive);
}

static int e100_dma_end(ide_drive_t *drive)
{
	/* TODO: check if something went wrong with the DMA */
	return 0;
}

static int e100_start_dma(ide_drive_t *drive, int atapi, int reading)
{
	if(reading) {

		RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
		WAIT_DMA(ATA_RX_DMA_NBR);

		/* set up the Etrax DMA descriptors */

		if(e100_ide_build_dmatable (drive))
			return 1;

		if(!atapi) {
			/* set the irq handler which will finish the request when DMA is done */

			ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);

			/* issue cmd to drive */
                        if ((HWGROUP(drive)->rq->cmd == IDE_DRIVE_TASKFILE) &&
			    (drive->addressing == 1)) {
				ide_task_t *args = HWGROUP(drive)->rq->special;
				etrax100_ide_outb(args->tfRegister[IDE_COMMAND_OFFSET], IDE_COMMAND_REG);
			} else if (drive->addressing) {
				etrax100_ide_outb(WIN_READDMA_EXT, IDE_COMMAND_REG);
			} else {
				etrax100_ide_outb(WIN_READDMA, IDE_COMMAND_REG);
			}
		}

		/* begin DMA */

		/* need to do this before RX DMA due to a chip bug
		 * it is enough to just flush the part of the cache that
		 * corresponds to the buffers we start, but since HD transfers
		 * usually are more than 8 kB, it is easier to optimize for the
		 * normal case and just flush the entire cache. its the only
		 * way to be sure! (OB movie quote)
		 */
		flush_etrax_cache();
		*R_DMA_CH3_FIRST = virt_to_phys(ata_descrs);
		*R_DMA_CH3_CMD   = IO_STATE(R_DMA_CH3_CMD, cmd, start);

		/* initiate a multi word dma read using DMA handshaking */

		*R_ATA_TRANSFER_CNT =
			IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);

		*R_ATA_CTRL_DATA =
			IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
			IO_STATE(R_ATA_CTRL_DATA, rw,       read) |
			IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma)  |
			IO_STATE(R_ATA_CTRL_DATA, handsh,   dma)  |
			IO_STATE(R_ATA_CTRL_DATA, multi,    on)   |
			IO_STATE(R_ATA_CTRL_DATA, dma_size, word);

		LED_DISK_READ(1);

		D(printk("dma read of %d bytes.\n", ata_tot_size));

	} else {
		/* writing */

		RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
		WAIT_DMA(ATA_TX_DMA_NBR);

		/* set up the Etrax DMA descriptors */

		if(e100_ide_build_dmatable (drive))
			return 1;

		if(!atapi) {
			/* set the irq handler which will finish the request when DMA is done */

			ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);

			/* issue cmd to drive */
			if ((HWGROUP(drive)->rq->cmd == IDE_DRIVE_TASKFILE) &&
			    (drive->addressing == 1)) {
				ide_task_t *args = HWGROUP(drive)->rq->special;
				etrax100_ide_outb(args->tfRegister[IDE_COMMAND_OFFSET], IDE_COMMAND_REG);
			} else if (drive->addressing) {
				etrax100_ide_outb(WIN_WRITEDMA_EXT, IDE_COMMAND_REG);
			} else {
				etrax100_ide_outb(WIN_WRITEDMA, IDE_COMMAND_REG);
			}
		}

		/* begin DMA */

		*R_DMA_CH2_FIRST = virt_to_phys(ata_descrs);
		*R_DMA_CH2_CMD   = IO_STATE(R_DMA_CH2_CMD, cmd, start);

		/* initiate a multi word dma write using DMA handshaking */

		*R_ATA_TRANSFER_CNT =
			IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);

		*R_ATA_CTRL_DATA =
			IO_FIELD(R_ATA_CTRL_DATA, data,     IDE_DATA_REG) |
			IO_STATE(R_ATA_CTRL_DATA, rw,       write) |
			IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma) |
			IO_STATE(R_ATA_CTRL_DATA, handsh,   dma) |
			IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
			IO_STATE(R_ATA_CTRL_DATA, dma_size, word);

		LED_DISK_WRITE(1);

		D(printk("dma write of %d bytes.\n", ata_tot_size));
	}
	return 0;
}

static int e100_dma_write(ide_drive_t *drive)
{
	e100_read_command = 0;
	/* ATAPI-devices (not disks) first call ide_dma_read/write to set the direction
	 * then they call ide_dma_begin after they have issued the appropriate drive command
	 * themselves to actually start the chipset DMA. so we just return here if we're
	 * not a diskdrive.
	 */
	if (drive->media != ide_disk)
                return 0;
	return e100_start_dma(drive, 0, 0);
}

static int e100_dma_read(ide_drive_t *drive)
{
	e100_read_command = 1;
	/* ATAPI-devices (not disks) first call ide_dma_read/write to set the direction
	 * then they call ide_dma_begin after they have issued the appropriate drive command
	 * themselves to actually start the chipset DMA. so we just return here if we're
	 * not a diskdrive.
	 */
	if (drive->media != ide_disk)
                return 0;
	return e100_start_dma(drive, 0, 1);
}

static int e100_dma_begin(ide_drive_t *drive)
{
	/* begin DMA, used by ATAPI devices which want to issue the
	 * appropriate IDE command themselves.
	 *
	 * they have already called ide_dma_read/write to set the
	 * static reading flag, now they call ide_dma_begin to do
	 * the real stuff. we tell our code below not to issue
	 * any IDE commands itself and jump into it.
	 */
	 return e100_start_dma(drive, 1, e100_read_command);
}