📄 viscopy.s
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VIS_enter: be,pt %xcc, dest_is_8byte_aligned ! CTI#ifdef __KERNEL__ nop ! IEU0 Group#else andcc %o0, 0x38, %g5 ! IEU1 Group#endifdo_dest_8byte_align: mov 8, %g1 ! IEU0 sub %g1, %g2, %g2 ! IEU0 Group andcc %o0, 1, %g0 ! IEU1 be,pt %icc, 2f ! CTI sub %o2, %g2, %o2 ! IEU0 Group1: ASI_SETSRC_NOBLK ! LSU Group EX(LDUB [%o1] ASINORMAL, %o5, add %o2, %g2) ! Load Group add %o1, 1, %o1 ! IEU0 add %o0, 1, %o0 ! IEU1 ASI_SETDST_NOBLK ! LSU Group subcc %g2, 1, %g2 ! IEU1 Group be,pn %xcc, 3f ! CTI EX2(STB %o5, [%o0 - 1] ASINORMAL, add %g2, 1, %g2, add %o2, %g2) ! Store2: ASI_SETSRC_NOBLK ! LSU Group EX(LDUB [%o1] ASINORMAL, %o5, add %o2, %g2) ! Load Group add %o0, 2, %o0 ! IEU0 EX2(LDUB [%o1 + 1] ASINORMAL, %g3, sub %o0, 2, %o0, add %o2, %g2) ! Load Group ASI_SETDST_NOBLK ! LSU Group subcc %g2, 2, %g2 ! IEU1 Group EX2(STB %o5, [%o0 - 2] ASINORMAL, add %g2, 2, %g2, add %o2, %g2) ! Store add %o1, 2, %o1 ! IEU0 bne,pt %xcc, 2b ! CTI Group EX2(STB %g3, [%o0 - 1] ASINORMAL, add %g2, 1, %g2, add %o2, %g2) ! Store#ifdef __KERNEL__3:dest_is_8byte_aligned: VISEntry andcc %o0, 0x38, %g5 ! IEU1 Group#else3: andcc %o0, 0x38, %g5 ! IEU1 Groupdest_is_8byte_aligned:#endif be,pt %icc, dest_is_64byte_aligned ! CTI mov 64, %g1 ! IEU0 fmovd %f0, %f2 ! FPU sub %g1, %g5, %g5 ! IEU0 Group ASI_SETSRC_NOBLK ! LSU Group alignaddr %o1, %g0, %g1 ! GRU Group EXO2(LDDF [%g1] ASINORMAL, %f4) ! Load Group sub %o2, %g5, %o2 ! IEU01: EX(LDDF [%g1 + 0x8] ASINORMAL, %f6, add %o2, %g5) ! Load Group add %g1, 0x8, %g1 ! IEU0 Group subcc %g5, 8, %g5 ! IEU1 ASI_SETDST_NOBLK ! LSU Group faligndata %f4, %f6, %f0 ! GRU Group EX2(STDF %f0, [%o0] ASINORMAL, add %g5, 8, %g5, add %o2, %g5) ! Store add %o1, 8, %o1 ! IEU0 Group be,pn %xcc, dest_is_64byte_aligned ! CTI add %o0, 8, %o0 ! IEU1 ASI_SETSRC_NOBLK ! LSU Group EX(LDDF [%g1 + 0x8] ASINORMAL, %f4, add %o2, %g5) ! Load Group add %g1, 8, %g1 ! IEU0 subcc %g5, 8, %g5 ! IEU1 ASI_SETDST_NOBLK ! LSU Group faligndata %f6, %f4, %f0 ! GRU Group EX2(STDF %f0, [%o0] ASINORMAL, add %g5, 8, %g5, add %o2, %g5) ! Store add %o1, 8, %o1 ! IEU0 ASI_SETSRC_NOBLK ! LSU Group bne,pt %xcc, 1b ! CTI Group add %o0, 8, %o0 ! IEU0dest_is_64byte_aligned: membar #LoadStore | #StoreStore | #StoreLoad ! LSU Group#ifndef __KERNEL__ wr %g0, ASI_BLK_P, %asi ! LSU Group#endif subcc %o2, 0x40, %g7 ! IEU1 Group mov %o1, %g1 ! IEU0 andncc %g7, (0x40 - 1), %g7 ! IEU1 Group srl %g1, 3, %g2 ! IEU0 sub %o2, %g7, %g3 ! IEU0 Group andn %o1, (0x40 - 1), %o1 ! IEU1 and %g2, 7, %g2 ! IEU0 Group andncc %g3, 0x7, %g3 ! IEU1 fmovd %f0, %f2 ! FPU sub %g3, 0x10, %g3 ! IEU0 Group sub %o2, %g7, %o2 ! IEU1#ifdef __KERNEL__ or asi_src, ASI_BLK_OR, asi_src ! IEU0 Group or asi_dest, ASI_BLK_OR, asi_dest ! IEU1#endif alignaddr %g1, %g0, %g0 ! GRU Group add %g1, %g7, %g1 ! IEU0 Group subcc %o2, %g3, %o2 ! IEU1 ASI_SETSRC_BLK ! LSU Group EXVIS1(LDBLK [%o1 + 0x00] ASIBLK, %f0) ! LSU Group add %g1, %g3, %g1 ! IEU0 EXVIS1(LDBLK [%o1 + 0x40] ASIBLK, %f16) ! LSU Group sub %g7, 0x80, %g7 ! IEU0 EXVIS(LDBLK [%o1 + 0x80] ASIBLK, %f32) ! LSU Group#ifdef __KERNEL__vispc: sll %g2, 9, %g2 ! IEU0 Group sethi %hi(vis00), %g5 ! IEU1 or %g5, %lo(vis00), %g5 ! IEU0 Group jmpl %g5 + %g2, %g0 ! CTI Group brk forced addcc %o1, 0xc0, %o1 ! IEU1 Group#else ! Clk1 Group 8-( ! Clk2 Group 8-( ! Clk3 Group 8-( ! Clk4 Group 8-(vispc: rd %pc, %g5 ! PDU Group 8-( addcc %g5, %lo(vis00 - vispc), %g5 ! IEU1 Group sll %g2, 9, %g2 ! IEU0 jmpl %g5 + %g2, %g0 ! CTI Group brk forced addcc %o1, 0xc0, %o1 ! IEU1 Group#endif .align 512 /* OK, here comes the fun part... */vis00:FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) LOOP_CHUNK1(o1, o0, g7, vis01) FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) LOOP_CHUNK2(o1, o0, g7, vis02) FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) LOOP_CHUNK3(o1, o0, g7, vis03) b,pt %xcc, vis00+4; faligndata %f0, %f2, %f48vis01:FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) STORE_JUMP(o0, f48, finish_f0) membar #Syncvis02:FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) STORE_JUMP(o0, f48, finish_f16) membar #Syncvis03:FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) STORE_JUMP(o0, f48, finish_f32) membar #Sync VISLOOP_PADvis10:FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) LOOP_CHUNK1(o1, o0, g7, vis11) FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) LOOP_CHUNK2(o1, o0, g7, vis12) FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) LOOP_CHUNK3(o1, o0, g7, vis13) b,pt %xcc, vis10+4; faligndata %f2, %f4, %f48vis11:FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) STORE_JUMP(o0, f48, finish_f2) membar #Syncvis12:FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) STORE_JUMP(o0, f48, finish_f18) membar #Syncvis13:FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) STORE_JUMP(o0, f48, finish_f34) membar #Sync VISLOOP_PADvis20:FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) LOOP_CHUNK1(o1, o0, g7, vis21) FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) LOOP_CHUNK2(o1, o0, g7, vis22) FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) LOOP_CHUNK3(o1, o0, g7, vis23) b,pt %xcc, vis20+4; faligndata %f4, %f6, %f48vis21:FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) STORE_JUMP(o0, f48, finish_f4) membar #Syncvis22:FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) STORE_JUMP(o0, f48, finish_f20) membar #Syncvis23:FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) STORE_JUMP(o0, f48, finish_f36) membar #Sync VISLOOP_PADvis30:FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) LOOP_CHUNK1(o1, o0, g7, vis31) FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) LOOP_CHUNK2(o1, o0, g7, vis32) FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) LOOP_CHUNK3(o1, o0, g7, vis33) b,pt %xcc, vis30+4; faligndata %f6, %f8, %f48vis31:FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) STORE_JUMP(o0, f48, finish_f6) membar #Syncvis32:FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) STORE_JUMP(o0, f48, finish_f22) membar #Syncvis33:FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) STORE_JUMP(o0, f48, finish_f38) membar #Sync VISLOOP_PADvis40:FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) LOOP_CHUNK1(o1, o0, g7, vis41) FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) LOOP_CHUNK2(o1, o0, g7, vis42) FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) LOOP_CHUNK3(o1, o0, g7, vis43) b,pt %xcc, vis40+4; faligndata %f8, %f10, %f48vis41:FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) STORE_JUMP(o0, f48, finish_f8) membar #Syncvis42:FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) STORE_JUMP(o0, f48, finish_f24) membar #Syncvis43:FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) STORE_JUMP(o0, f48, finish_f40) membar #Sync VISLOOP_PADvis50:FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) LOOP_CHUNK1(o1, o0, g7, vis51) FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) LOOP_CHUNK2(o1, o0, g7, vis52) FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) LOOP_CHUNK3(o1, o0, g7, vis53) b,pt %xcc, vis50+4; faligndata %f10, %f12, %f48vis51:FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) STORE_JUMP(o0, f48, finish_f10) membar #Syncvis52:FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) STORE_JUMP(o0, f48, finish_f26) membar #Syncvis53:FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) STORE_JUMP(o0, f48, finish_f42) membar #Sync VISLOOP_PADvis60:FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) LOOP_CHUNK1(o1, o0, g7, vis61) FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) LOOP_CHUNK2(o1, o0, g7, vis62) FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) LOOP_CHUNK3(o1, o0, g7, vis63) b,pt %xcc, vis60+4; faligndata %f12, %f14, %f48vis61:FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) STORE_JUMP(o0, f48, finish_f12) membar #Syncvis62:FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) STORE_JUMP(o0, f48, finish_f28) membar #Syncvis63:FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) STORE_JUMP(o0, f48, finish_f44) membar #Sync VISLOOP_PADvis70:FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) LOOP_CHUNK1(o1, o0, g7, vis71) FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) LOOP_CHUNK2(o1, o0, g7, vis72) FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) LOOP_CHUNK3(o1, o0, g7, vis73) b,pt %xcc, vis70+4; faligndata %f14, %f16, %f48vis71:FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) STORE_JUMP(o0, f48, finish_f14) membar #Syncvis72:FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) STORE_JUMP(o0, f48, finish_f30) membar #Syncvis73:FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) STORE_SYNC(o0, f48) membar #Sync FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) STORE_JUMP(o0, f48, finish_f46) membar #Sync VISLOOP_PADfinish_f0: FINISH_VISCHUNK(o0, f0, f2, g3)finish_f2: FINISH_VISCHUNK(o0, f2, f4, g3)finish_f4: FINISH_VISCHUNK(o0, f4, f6, g3)finish_f6: FINISH_VISCHUNK(o0, f6, f8, g3)finish_f8: FINISH_VISCHUNK(o0, f8, f10, g3)finish_f10: FINISH_VISCHUNK(o0, f10, f12, g3)finish_f12: FINISH_VISCHUNK(o0, f12, f14, g3)finish_f14: UNEVEN_VISCHUNK(o0, f14, f0, g3)finish_f16: FINISH_VISCHUNK(o0, f16, f18, g3)finish_f18: FINISH_VISCHUNK(o0, f18, f20, g3)finish_f20: FINISH_VISCHUNK(o0, f20, f22, g3)finish_f22: FINISH_VISCHUNK(o0, f22, f24, g3)finish_f24: FINISH_VISCHUNK(o0, f24, f26, g3)finish_f26: FINISH_VISCHUNK(o0, f26, f28, g3)finish_f28: FINISH_VISCHUNK(o0, f28, f30, g3)finish_f30: UNEVEN_VISCHUNK(o0, f30, f0, g3)finish_f32: FINISH_VISCHUNK(o0, f32, f34, g3)finish_f34: FINISH_VISCHUNK(o0, f34, f36, g3)finish_f36: FINISH_VISCHUNK(o0, f36, f38, g3)finish_f38: FINISH_VISCHUNK(o0, f38, f40, g3)finish_f40: FINISH_VISCHUNK(o0, f40, f42, g3)finish_f42: FINISH_VISCHUNK(o0, f42, f44, g3)finish_f44: FINISH_VISCHUNK(o0, f44, f46, g3)finish_f46: UNEVEN_VISCHUNK_LAST(o0, f46, f0, g3)vis_out_slk:#ifdef __KERNEL__ srl asi_src, 3, %g5 ! IEU0 Group xor asi_src, ASI_BLK_XOR1, asi_src ! IEU1 xor asi_src, %g5, asi_src ! IEU0 Group#endifvis_slk:ASI_SETSRC_NOBLK ! LSU Group EXVIS3(LDDF [%o1] ASINORMAL, %f2) ! Load Group add %o1, 8, %o1 ! IEU0 subcc %g3, 8, %g3 ! IEU1 ASI_SETDST_NOBLK ! LSU Group faligndata %f0, %f2, %f8 ! GRU Group EXVIS4(STDF %f8, [%o0] ASINORMAL) ! Store bl,pn %xcc, vis_out_slp ! CTI add %o0, 8, %o0 ! IEU0 Group ASI_SETSRC_NOBLK ! LSU Group EXVIS3(LDDF [%o1] ASINORMAL, %f0) ! Load Group add %o1, 8, %o1 ! IEU0 subcc %g3, 8, %g3 ! IEU1 ASI_SETDST_NOBLK ! LSU Group faligndata %f2, %f0, %f8 ! GRU Group EXVIS4(STDF %f8, [%o0] ASINORMAL) ! Store bge,pt %xcc, vis_slk ! CTI add %o0, 8, %o0 ! IEU0 Groupvis_out_slp:#ifdef __KERNEL__ brz,pt %o2, vis_ret ! CTI Group mov %g1, %o1 ! IEU0 ba,pt %xcc, vis_slp+4 ! CTI Group ASI_SETSRC_NOBLK ! LSU Group#endifvis_out:brz,pt %o2, vis_ret ! CTI Group mov %g1, %o1 ! IEU0#ifdef __KERNEL__ srl asi_src, 3, %g5 ! IEU0 Group xor asi_src, ASI_BLK_XOR1, asi_src ! IEU1 xor asi_src, %g5, asi_src ! IEU0 Group#endifvis_slp:ASI_SETSRC_NOBLK ! LSU Group EXO2(LDUB [%o1] ASINORMAL, %g5) ! LOAD add %o1, 1, %o1 ! IEU0 add %o0, 1, %o0 ! IEU1 ASI_SETDST_NOBLK ! LSU Group subcc %o2, 1, %o2 ! IEU1 bne,pt %xcc, vis_slp ! CTI EX(STB %g5, [%o0 - 1] ASINORMAL, add %o2, 1) ! Store Groupvis_ret:membar #StoreLoad | #StoreStore ! LSU Group FPU_CLEAN_RETL__memcpy_short: andcc %o2, 1, %g0 ! IEU1 Group be,pt %icc, 2f ! CTI1: ASI_SETSRC_NOBLK ! LSU Group EXO2(LDUB [%o1] ASINORMAL, %g5) ! LOAD Group add %o1, 1, %o1 ! IEU0 add %o0, 1, %o0 ! IEU1 ASI_SETDST_NOBLK ! LSU Group subcc %o2, 1, %o2 ! IEU1 Group be,pn %xcc, short_ret ! CTI EX(STB %g5, [%o0 - 1] ASINORMAL, add %o2, 1) ! Store2: ASI_SETSRC_NOBLK ! LSU Group EXO2(LDUB [%o1] ASINORMAL, %g5) ! LOAD Group add %o0, 2, %o0 ! IEU0 EX2(LDUB [%o1 + 1] ASINORMAL, %o5, sub %o0, 2, %o0, add %o2, %g0) ! LOAD Group add %o1, 2, %o1 ! IEU0 ASI_SETDST_NOBLK ! LSU Group subcc %o2, 2, %o2 ! IEU1 Group EX(STB %g5, [%o0 - 2] ASINORMAL, add %o2, 2) ! Store bne,pt %xcc, 2b ! CTI EX(STB %o5, [%o0 - 1] ASINORMAL, add %o2, 1) ! Storeshort_ret: NORMAL_RETL#ifndef __KERNEL__memcpy_private:memcpy:#ifndef REGS_64BIT srl %o2, 0, %o2 ! IEU1 Group#endif brz,pn %o2, short_ret ! CTI Group mov %o0, %g6 ! IEU0#endif__memcpy_entry: cmp %o2, 15 ! IEU1 Group bleu,pn %xcc, __memcpy_short ! CTI cmp %o2, (64 * 6) ! IEU1 Group bgeu,pn %xcc, VIS_enter ! CTI andcc %o0, 7, %g2 ! IEU1 Group sub %o0, %o1, %g5 ! IEU0 andcc %g5, 3, %o5 ! IEU1 Group bne,pn %xcc, memcpy_noVIS_misaligned ! CTI andcc %o1, 3, %g0 ! IEU1 Group#ifdef REGS_64BIT be,a,pt %xcc, 3f ! CTI andcc %o1, 4, %g0 ! IEU1 Group andcc %o1, 1, %g0 ! IEU1 Group#else /* !REGS_64BIT */ be,pt %xcc, 5f ! CTI andcc %o1, 1, %g0 ! IEU1 Group#endif /* !REGS_64BIT */ be,pn %xcc, 4f ! CTI andcc %o1, 2, %g0 ! IEU1 Group ASI_SETSRC_NOBLK ! LSU Group EXO2(LDUB [%o1] ASINORMAL, %g2) ! Load Group add %o1, 1, %o1 ! IEU0 add %o0, 1, %o0 ! IEU1 sub %o2, 1, %o2 ! IEU0 Group ASI_SETDST_NOBLK ! LSU Group bne,pn %xcc, 5f ! CTI Group EX(STB %g2, [%o0 - 1] ASINORMAL, add %o2, 1) ! Store4: ASI_SETSRC_NOBLK ! LSU Group EXO2(LDUH [%o1] ASINORMAL, %g2) ! Load Group add %o1, 2, %o1 ! IEU0 add %o0, 2, %o0 ! IEU1 ASI_SETDST_NOBLK ! LSU Group sub %o2, 2, %o2 ! IEU0 EX(STH %g2, [%o0 - 2] ASINORMAL, add %o2, 2) ! Store Group + bubble#ifdef REGS_64BIT5: andcc %o1, 4, %g0 ! IEU13: be,a,pn %xcc, 2f ! CTI andcc %o2, -128, %g7 ! IEU1 Group ASI_SETSRC_NOBLK ! LSU Group EXO2(LDUW [%o1] ASINORMAL, %g5) ! Load Group add %o1, 4, %o1 ! IEU0 add %o0, 4, %o0 ! IEU1 ASI_SETDST_NOBLK ! LSU Group sub %o2, 4, %o2 ! IEU0 Group EX(STW %g5, [%o0 - 4] ASINORMAL,⌨️ 快捷键说明
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