📄 mm-armv.c
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{ struct cachepolicy *cp; unsigned int cr = get_cr(); int cpu_arch = cpu_architecture(); int i;#if defined(CONFIG_CPU_DCACHE_DISABLE) if (cachepolicy > CPOLICY_BUFFERED) cachepolicy = CPOLICY_BUFFERED;#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) if (cachepolicy > CPOLICY_WRITETHROUGH) cachepolicy = CPOLICY_WRITETHROUGH;#endif if (cpu_arch < CPU_ARCH_ARMv5) { if (cachepolicy >= CPOLICY_WRITEALLOC) cachepolicy = CPOLICY_WRITEBACK; ecc_mask = 0; } if (cpu_arch <= CPU_ARCH_ARMv5) { mem_types[MT_DEVICE].prot_l1 |= PMD_BIT4; mem_types[MT_DEVICE].prot_sect |= PMD_BIT4; mem_types[MT_CACHECLEAN].prot_sect |= PMD_BIT4; mem_types[MT_MINICLEAN].prot_sect |= PMD_BIT4; mem_types[MT_VECTORS].prot_l1 |= PMD_BIT4; mem_types[MT_MEMORY].prot_sect |= PMD_BIT4; } /* * ARMv6 and above have extended page tables. */ if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { /* * bit 4 becomes XN which we must clear for the * kernel memory mapping. */ mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4; /* * Mark cache clean areas read only from SVC mode * and no access from userspace. */ mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; } cp = &cache_policies[cachepolicy]; if (cpu_arch >= CPU_ARCH_ARMv5) { mem_types[MT_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE; } else { mem_types[MT_VECTORS].prot_pte |= cp->pte; mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); } mem_types[MT_VECTORS].prot_l1 |= ecc_mask; mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; for (i = 0; i < 16; i++) { unsigned long v = pgprot_val(protection_map[i]); v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | cp->pte; protection_map[i] = __pgprot(v); } pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_WRITE | L_PTE_EXEC | cp->pte); switch (cp->pmd) { case PMD_SECT_WT: mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; break; case PMD_SECT_WB: case PMD_SECT_WBWA: mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; break; } printk("Memory policy: ECC %sabled, Data cache %s\n", ecc_mask ? "en" : "dis", cp->policy);}/* * Create the page directory entries and any necessary * page tables for the mapping specified by `md'. We * are able to cope here with varying sizes and address * offsets, and we take full advantage of sections. */static void __init create_mapping(struct map_desc *md){ unsigned long virt, length; int prot_sect, prot_l1, domain; pgprot_t prot_pte; long off; if (md->virtual != vectors_base() && md->virtual < PAGE_OFFSET) { printk(KERN_WARNING "BUG: not creating mapping for " "0x%08lx at 0x%08lx in user region\n", md->physical, md->virtual); return; } if (md->type == MT_DEVICE && md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { printk(KERN_WARNING "BUG: mapping for 0x%08lx at 0x%08lx " "overlaps vmalloc space\n", md->physical, md->virtual); } domain = mem_types[md->type].domain; prot_pte = __pgprot(mem_types[md->type].prot_pte); prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain); prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain); virt = md->virtual; off = md->physical - virt; length = md->length; if (mem_types[md->type].prot_l1 == 0 && (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) { printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " "be mapped using pages, ignoring.\n", md->physical, md->virtual); return; } while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) { alloc_init_page(virt, virt + off, prot_l1, prot_pte); virt += PAGE_SIZE; length -= PAGE_SIZE; } while (length >= (PGDIR_SIZE / 2)) { alloc_init_section(virt, virt + off, prot_sect); virt += (PGDIR_SIZE / 2); length -= (PGDIR_SIZE / 2); } while (length >= PAGE_SIZE) { alloc_init_page(virt, virt + off, prot_l1, prot_pte); virt += PAGE_SIZE; length -= PAGE_SIZE; }}/* * In order to soft-boot, we need to insert a 1:1 mapping in place of * the user-mode pages. This will then ensure that we have predictable * results when turning the mmu off */void setup_mm_for_reboot(char mode){ unsigned long pmdval; pgd_t *pgd; pmd_t *pmd; int i; int cpu_arch = cpu_architecture(); if (current->mm && current->mm->pgd) pgd = current->mm->pgd; else pgd = init_mm.pgd; for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) { pmdval = (i << PGDIR_SHIFT) | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; if (cpu_arch <= CPU_ARCH_ARMv5) pmdval |= PMD_BIT4; pmd = pmd_offset(pgd + i, i << PGDIR_SHIFT); set_pmd(pmd, __pmd(pmdval)); }}/* * Setup initial mappings. We use the page we allocated for zero page to hold * the mappings, which will get overwritten by the vectors in traps_init(). * The mappings must be in virtual address order. */void __init memtable_init(struct meminfo *mi){ struct map_desc *init_maps, *p, *q; unsigned long address = 0; int i; build_mem_type_table(); init_maps = p = alloc_bootmem_low_pages(PAGE_SIZE); for (i = 0; i < mi->nr_banks; i++) { if (mi->bank[i].size == 0) continue; p->physical = mi->bank[i].start; p->virtual = __phys_to_virt(p->physical); p->length = mi->bank[i].size; p->type = MT_MEMORY; p ++; }#ifdef FLUSH_BASE p->physical = FLUSH_BASE_PHYS; p->virtual = FLUSH_BASE; p->length = PGDIR_SIZE; p->type = MT_CACHECLEAN; p ++;#endif#ifdef FLUSH_BASE_MINICACHE p->physical = FLUSH_BASE_PHYS + PGDIR_SIZE; p->virtual = FLUSH_BASE_MINICACHE; p->length = PGDIR_SIZE; p->type = MT_MINICLEAN; p ++;#endif /* * Go through the initial mappings, but clear out any * pgdir entries that are not in the description. */ q = init_maps; do { if (address < q->virtual || q == p) { clear_mapping(address); address += PGDIR_SIZE; } else { create_mapping(q); address = q->virtual + q->length; address = (address + PGDIR_SIZE - 1) & PGDIR_MASK; q ++; } } while (address != 0); /* * Create a mapping for the machine vectors at virtual address 0 * or 0xffff0000. We should always try the high mapping. */ init_maps->physical = virt_to_phys(init_maps); init_maps->virtual = vectors_base(); init_maps->length = PAGE_SIZE; init_maps->type = MT_VECTORS; create_mapping(init_maps); flush_cache_all(); flush_tlb_all();}/* * Create the architecture specific mappings */void __init iotable_init(struct map_desc *io_desc, int nr){ int i; for (i = 0; i < nr; i++) create_mapping(io_desc + i);}static inline voidfree_memmap(int node, unsigned long start_pfn, unsigned long end_pfn){ struct page *start_pg, *end_pg; unsigned long pg, pgend; /* * Convert start_pfn/end_pfn to a struct page pointer. */ start_pg = pfn_to_page(start_pfn); end_pg = pfn_to_page(end_pfn); /* * Convert to physical addresses, and * round start upwards and end downwards. */ pg = PAGE_ALIGN(__pa(start_pg)); pgend = __pa(end_pg) & PAGE_MASK; /* * If there are free pages between these, * free the section of the memmap array. */ if (pg < pgend) free_bootmem_node(NODE_DATA(node), pg, pgend - pg);}static inline void free_unused_memmap_node(int node, struct meminfo *mi){ unsigned long bank_start, prev_bank_end = 0; unsigned int i; /* * [FIXME] This relies on each bank being in address order. This * may not be the case, especially if the user has provided the * information on the command line. */ for (i = 0; i < mi->nr_banks; i++) { if (mi->bank[i].size == 0 || mi->bank[i].node != node) continue; bank_start = mi->bank[i].start >> PAGE_SHIFT; if (bank_start < prev_bank_end) { printk(KERN_ERR "MEM: unordered memory banks. " "Not freeing memmap.\n"); break; } /* * If we had a previous bank, and there is a space * between the current bank and the previous, free it. */ if (prev_bank_end && prev_bank_end != bank_start) free_memmap(node, prev_bank_end, bank_start); prev_bank_end = PAGE_ALIGN(mi->bank[i].start + mi->bank[i].size) >> PAGE_SHIFT; }}/* * The mem_map array can get very big. Free * the unused area of the memory map. */void __init create_memmap_holes(struct meminfo *mi){ int node; for (node = 0; node < numnodes; node++) free_unused_memmap_node(node, mi);}
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