ads7846.qsf

四线电阻式触摸屏

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ads7846_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name TOP_LEVEL_ENTITY Block1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:32:43  MARCH 11, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name VHDL_FILE ads7846.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE ads7846.vwf
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name VHDL_FILE ads7846a.vhd
set_global_assignment -name VHDL_FILE fenpin.vhd
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE ads7846.vwf
set_global_assignment -name BDF_FILE Block1.bdf
set_location_assignment PIN_107 -to dclk
set_location_assignment PIN_106 -to cs
set_location_assignment PIN_105 -to din
set_location_assignment PIN_104 -to busy
set_location_assignment PIN_103 -to dout
set_location_assignment PIN_102 -to penir
set_location_assignment PIN_18 -to clk
set_location_assignment PIN_131 -to xdou[11]
set_location_assignment PIN_130 -to xdou[10]
set_location_assignment PIN_129 -to xdou[9]
set_location_assignment PIN_127 -to xdou[8]
set_location_assignment PIN_125 -to xdou[7]
set_location_assignment PIN_124 -to xdou[6]
set_location_assignment PIN_123 -to xdou[5]
set_location_assignment PIN_122 -to xdou[4]
set_location_assignment PIN_96 -to a
set_location_assignment PIN_95 -to b
set_location_assignment PIN_94 -to c
set_location_assignment PIN_93 -to d
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"