📄 ads7846.sim.rpt
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; |ADS7846a|state.control ; |ADS7846a|state.control ; regout ;
; |ADS7846a|Selector10~30 ; |ADS7846a|Selector10~30 ; combout ;
; |ADS7846a|cnt1[0] ; |ADS7846a|cnt1[0]~125 ; cout0 ;
; |ADS7846a|cnt1[0] ; |ADS7846a|cnt1[0]~125COUT1 ; cout1 ;
; |ADS7846a|cnt1[1] ; |ADS7846a|cnt1[1]~127 ; cout0 ;
; |ADS7846a|cnt1[1] ; |ADS7846a|cnt1[1]~127COUT1 ; cout1 ;
; |ADS7846a|cnt1[2] ; |ADS7846a|cnt1[2]~129 ; cout0 ;
; |ADS7846a|cnt1[2] ; |ADS7846a|cnt1[2]~129COUT1 ; cout1 ;
; |ADS7846a|cnt1[3] ; |ADS7846a|cnt1[3]~131 ; cout0 ;
; |ADS7846a|cnt1[3] ; |ADS7846a|cnt1[3]~131COUT1 ; cout1 ;
; |ADS7846a|Equal1~41 ; |ADS7846a|Equal1~41 ; combout ;
; |ADS7846a|Selector15~13 ; |ADS7846a|Selector15~13 ; combout ;
; |ADS7846a|Equal4~26 ; |ADS7846a|Equal4~26 ; combout ;
; |ADS7846a|cnt2[2] ; |ADS7846a|cnt2[2] ; regout ;
; |ADS7846a|cnt2[3] ; |ADS7846a|cnt2[3] ; regout ;
; |ADS7846a|cnt2[0] ; |ADS7846a|cnt2[0] ; regout ;
; |ADS7846a|cnt2[1] ; |ADS7846a|Equal0~87 ; combout ;
; |ADS7846a|cnt2[1] ; |ADS7846a|cnt2[1] ; regout ;
; |ADS7846a|cnt2[8] ; |ADS7846a|cnt2[8] ; regout ;
; |ADS7846a|cnt2[5] ; |ADS7846a|cnt2[5] ; regout ;
; |ADS7846a|cnt2[6] ; |ADS7846a|cnt2[6] ; regout ;
; |ADS7846a|cnt2[7] ; |ADS7846a|cnt2[7] ; regout ;
; |ADS7846a|cnt2[4] ; |ADS7846a|Equal0~88 ; combout ;
; |ADS7846a|cnt2[4] ; |ADS7846a|cnt2[4] ; regout ;
; |ADS7846a|Selector13~17 ; |ADS7846a|Selector13~17 ; combout ;
; |ADS7846a|write_cnt[2]~110 ; |ADS7846a|write_cnt[2]~110 ; combout ;
; |ADS7846a|cnt1[0]~134 ; |ADS7846a|cnt1[0]~134 ; combout ;
; |ADS7846a|Add1~132 ; |ADS7846a|Add1~132 ; combout ;
; |ADS7846a|Add1~132 ; |ADS7846a|Add1~133 ; cout0 ;
; |ADS7846a|Add1~132 ; |ADS7846a|Add1~133COUT1 ; cout1 ;
; |ADS7846a|Add1~134 ; |ADS7846a|Add1~134 ; combout ;
; |ADS7846a|Add1~134 ; |ADS7846a|Add1~135 ; cout0 ;
; |ADS7846a|Add1~134 ; |ADS7846a|Add1~135COUT1 ; cout1 ;
; |ADS7846a|Add1~136 ; |ADS7846a|Add1~136 ; combout ;
; |ADS7846a|Add1~136 ; |ADS7846a|Add1~137 ; cout0 ;
; |ADS7846a|Add1~136 ; |ADS7846a|Add1~137COUT1 ; cout1 ;
; |ADS7846a|Add1~138 ; |ADS7846a|Add1~138 ; combout ;
; |ADS7846a|Add1~138 ; |ADS7846a|Add1~139 ; cout0 ;
; |ADS7846a|Add1~138 ; |ADS7846a|Add1~139COUT1 ; cout1 ;
; |ADS7846a|Add1~140 ; |ADS7846a|Add1~140 ; combout ;
; |ADS7846a|Add1~142 ; |ADS7846a|Add1~142 ; combout ;
; |ADS7846a|Add1~142 ; |ADS7846a|Add1~143COUT1 ; cout1 ;
; |ADS7846a|Add1~144 ; |ADS7846a|Add1~144 ; combout ;
; |ADS7846a|Add1~144 ; |ADS7846a|Add1~145 ; cout ;
; |ADS7846a|Add1~146 ; |ADS7846a|Add1~146 ; combout ;
; |ADS7846a|Add1~146 ; |ADS7846a|Add1~147COUT1 ; cout1 ;
; |ADS7846a|Add1~148 ; |ADS7846a|Add1~148 ; combout ;
; |ADS7846a|Add1~148 ; |ADS7846a|Add1~149COUT1 ; cout1 ;
; |ADS7846a|Selector7~128 ; |ADS7846a|Selector7~128 ; combout ;
; |ADS7846a|pen ; |ADS7846a|pen ; combout ;
; |ADS7846a|wait_flag ; |ADS7846a|wait_flag ; combout ;
; |ADS7846a|clk2mhz ; |ADS7846a|clk2mhz~corein ; combout ;
; |ADS7846a|dout ; |ADS7846a|dout~corein ; combout ;
; |ADS7846a|clk1khz ; |ADS7846a|clk1khz~corein ; combout ;
; |ADS7846a|penirq ; |ADS7846a|penirq~corein ; combout ;
; |ADS7846a|din ; |ADS7846a|din ; padio ;
; |ADS7846a|dclk ; |ADS7846a|dclk ; padio ;
; |ADS7846a|cs ; |ADS7846a|cs ; padio ;
+----------------------------+----------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------+--------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------+--------------------+------------------+
; |ADS7846a|Add1~142 ; |ADS7846a|Add1~143 ; cout0 ;
; |ADS7846a|Add1~146 ; |ADS7846a|Add1~147 ; cout0 ;
; |ADS7846a|Add1~148 ; |ADS7846a|Add1~149 ; cout0 ;
+--------------------+--------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+----------------------------+----------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------+----------------------------+------------------+
; |ADS7846a|write_control[4] ; |ADS7846a|write_control[4] ; regout ;
; |ADS7846a|Add1~142 ; |ADS7846a|Add1~143 ; cout0 ;
; |ADS7846a|Add1~146 ; |ADS7846a|Add1~147 ; cout0 ;
; |ADS7846a|Add1~148 ; |ADS7846a|Add1~149 ; cout0 ;
; |ADS7846a|xdout[0] ; |ADS7846a|xdout[0] ; padio ;
; |ADS7846a|xdout[1] ; |ADS7846a|xdout[1] ; padio ;
; |ADS7846a|xdout[2] ; |ADS7846a|xdout[2] ; padio ;
; |ADS7846a|xdout[3] ; |ADS7846a|xdout[3] ; padio ;
; |ADS7846a|xdout[4] ; |ADS7846a|xdout[4] ; padio ;
; |ADS7846a|xdout[5] ; |ADS7846a|xdout[5] ; padio ;
; |ADS7846a|xdout[6] ; |ADS7846a|xdout[6] ; padio ;
; |ADS7846a|xdout[7] ; |ADS7846a|xdout[7] ; padio ;
; |ADS7846a|xdout[8] ; |ADS7846a|xdout[8] ; padio ;
; |ADS7846a|xdout[9] ; |ADS7846a|xdout[9] ; padio ;
; |ADS7846a|xdout[10] ; |ADS7846a|xdout[10] ; padio ;
; |ADS7846a|xdout[11] ; |ADS7846a|xdout[11] ; padio ;
; |ADS7846a|ydout[0] ; |ADS7846a|ydout[0] ; padio ;
; |ADS7846a|ydout[1] ; |ADS7846a|ydout[1] ; padio ;
; |ADS7846a|ydout[2] ; |ADS7846a|ydout[2] ; padio ;
; |ADS7846a|ydout[3] ; |ADS7846a|ydout[3] ; padio ;
; |ADS7846a|ydout[4] ; |ADS7846a|ydout[4] ; padio ;
; |ADS7846a|ydout[5] ; |ADS7846a|ydout[5] ; padio ;
; |ADS7846a|ydout[6] ; |ADS7846a|ydout[6] ; padio ;
; |ADS7846a|ydout[7] ; |ADS7846a|ydout[7] ; padio ;
; |ADS7846a|ydout[8] ; |ADS7846a|ydout[8] ; padio ;
; |ADS7846a|ydout[9] ; |ADS7846a|ydout[9] ; padio ;
; |ADS7846a|ydout[10] ; |ADS7846a|ydout[10] ; padio ;
; |ADS7846a|ydout[11] ; |ADS7846a|ydout[11] ; padio ;
+----------------------------+----------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
Info: Processing started: Wed Mar 18 15:32:12 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off ads7846 -c ads7846
Info: Using vector source file "D:/Altera/72/quartus/ads7846/ads7846.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 75.00 %
Info: Number of transitions in simulation is 4046863
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 103 megabytes of memory during processing
Info: Processing ended: Wed Mar 18 15:37:39 2009
Info: Elapsed time: 00:05:27
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