prev_cmp_ads7846.tan.qmsg

四线电阻式触摸屏

{ "Info" "ITDB_FULL_TPD_RESULT" "clk2mhz dclk 8.419 ns Longest " "Info: Longest tpd from source pin \"clk2mhz\" to destination pin \"dclk\" is 8.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk2mhz 1 CLK PIN_18 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 30; CLK Node = 'clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2mhz } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.576 ns) + CELL(0.511 ns) 4.250 ns dclk~9 2 COMB LC_X15_Y9_N5 1 " "Info: 2: + IC(2.576 ns) + CELL(0.511 ns) = 4.250 ns; Loc. = LC_X15_Y9_N5; Fanout = 1; COMB Node = 'dclk~9'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.087 ns" { clk2mhz dclk~9 } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.847 ns) + CELL(2.322 ns) 8.419 ns dclk 3 PIN PIN_107 0 " "Info: 3: + IC(1.847 ns) + CELL(2.322 ns) = 8.419 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'dclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.169 ns" { dclk~9 dclk } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.996 ns ( 47.46 % ) " "Info: Total cell delay = 3.996 ns ( 47.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.423 ns ( 52.54 % ) " "Info: Total interconnect delay = 4.423 ns ( 52.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk2mhz dclk~9 dclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk2mhz {} clk2mhz~combout {} dclk~9 {} dclk {} } { 0.000ns 0.000ns 2.576ns 1.847ns } { 0.000ns 1.163ns 0.511ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "dataoutx\[4\] dout clk2mhz -1.319 ns register " "Info: th for register \"dataoutx\[4\]\" (data pin = \"dout\", clock pin = \"clk2mhz\") is -1.319 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2mhz destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk2mhz\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk2mhz 1 CLK PIN_18 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 30; CLK Node = 'clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2mhz } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns dataoutx\[4\] 2 REG LC_X12_Y7_N9 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y7_N9; Fanout = 2; REG Node = 'dataoutx\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk2mhz dataoutx[4] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk2mhz dataoutx[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk2mhz {} clk2mhz~combout {} dataoutx[4] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.359 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns dout 1 PIN PIN_103 12 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_103; Fanout = 12; PIN Node = 'dout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.044 ns) + CELL(1.183 ns) 5.359 ns dataoutx\[4\] 2 REG LC_X12_Y7_N9 2 " "Info: 2: + IC(3.044 ns) + CELL(1.183 ns) = 5.359 ns; Loc. = LC_X12_Y7_N9; Fanout = 2; REG Node = 'dataoutx\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.227 ns" { dout dataoutx[4] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 43.20 % ) " "Info: Total cell delay = 2.315 ns ( 43.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.044 ns ( 56.80 % ) " "Info: Total interconnect delay = 3.044 ns ( 56.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { dout dataoutx[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.359 ns" { dout {} dout~combout {} dataoutx[4] {} } { 0.000ns 0.000ns 3.044ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk2mhz dataoutx[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk2mhz {} clk2mhz~combout {} dataoutx[4] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { dout dataoutx[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.359 ns" { dout {} dout~combout {} dataoutx[4] {} } { 0.000ns 0.000ns 3.044ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 5 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 18 22:33:07 2009 " "Info: Processing ended: Wed Mar 18 22:33:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}