prev_cmp_ads7846.tan.qmsg

四线电阻式触摸屏

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "wait_flag " "Warning: Node \"wait_flag\" is a latch" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "pen " "Warning: Node \"pen\" is a latch" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 20 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2mhz " "Info: Assuming node \"clk2mhz\" is an undefined clock" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 9 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2mhz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1khz " "Info: Assuming node \"clk1khz\" is an undefined clock" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 9 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "state.wait_300ms " "Info: Detected ripple clock \"state.wait_300ms\" as buffer" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "state.wait_300ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "state.reset " "Info: Detected ripple clock \"state.reset\" as buffer" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "state.reset" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}