📄 ads7846.map.rpt
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; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+--------------+
; |Block1 ; 117 (0) ; 61 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 ; 0 ; 56 (0) ; 6 (0) ; 55 (0) ; 25 (0) ; 0 (0) ; |Block1 ; work ;
; |ADS7846a:inst| ; 81 (81) ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 38 (38) ; 6 (6) ; 37 (37) ; 14 (14) ; 0 (0) ; |Block1|ADS7846a:inst ; work ;
; |fenpin:inst1| ; 36 (36) ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (18) ; 0 (0) ; 18 (18) ; 11 (11) ; 0 (0) ; |Block1|fenpin:inst1 ; work ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------------------+
; State Machine - |Block1|ADS7846a:inst|state ;
+------------------+------------------+----------------+-----------------+---------------+-------------+
; Name ; state.wait_300ms ; state.read_bit ; state.write_bit ; state.control ; state.reset ;
+------------------+------------------+----------------+-----------------+---------------+-------------+
; state.reset ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.control ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.write_bit ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.read_bit ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.wait_300ms ; 1 ; 0 ; 0 ; 0 ; 1 ;
+------------------+------------------+----------------+-----------------+---------------+-------------+
+--------------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+--------------------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+--------------------------------+------------------------+
; ADS7846a:inst|wait_flag ; ADS7846a:inst|state.reset ; yes ;
; ADS7846a:inst|pen ; ADS7846a:inst|state.wait_300ms ; yes ;
; Number of user-specified and inferred latches = 2 ; ; ;
+----------------------------------------------------+--------------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+--------------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+--------------------------------------------+
; ADS7846a:inst|write_control[0..3,5] ; Stuck at GND due to stuck port data_in ;
; ADS7846a:inst|write_control[4] ; Merged with ADS7846a:inst|write_control[7] ;
; Total Number of Removed Registers = 6 ; ;
+---------------------------------------+--------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 61 ;
; Number of registers using Synchronous Clear ; 5 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 14 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |Block1|fenpin:inst1|cnt1[4] ;
; 3:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |Block1|fenpin:inst1|cnt2[5] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |Block1|ADS7846a:inst|cnt1[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
Info: Processing started: Wed Mar 18 22:33:29 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ads7846 -c ads7846
Info: Found 2 design units, including 1 entities, in source file ads7846.vhd
Info: Found design unit 1: ads7846-behavioral
Info: Found entity 1: ADS7846
Info: Found 2 design units, including 1 entities, in source file ads7846a.vhd
Info: Found design unit 1: ads7846a-behavioral
Info: Found entity 1: ADS7846a
Info: Found 2 design units, including 1 entities, in source file fenpin.vhd
Info: Found design unit 1: fenpin-behav
Info: Found entity 1: fenpin
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
Info: Found entity 1: Block1
Info: Elaborating entity "Block1" for the top level hierarchy
Info: Elaborating entity "ADS7846a" for hierarchy "ADS7846a:inst"
Warning (10036): Verilog HDL or VHDL warning at ads7846a.vhd(25): object "dataouty" assigned a value but never read
Warning (10492): VHDL Process Statement warning at ads7846a.vhd(47): signal "cnt1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ads7846a.vhd(50): signal "cnt2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at ads7846a.vhd(44): inferring latch(es) for signal or variable "pen", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ads7846a.vhd(44): inferring latch(es) for signal or variable "wait_flag", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at ads7846a.vhd(59): signal "clk2mhz" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10034): Output port "a" at ads7846a.vhd(11) has no driver
Warning (10034): Output port "b" at ads7846a.vhd(11) has no driver
Warning (10034): Output port "c" at ads7846a.vhd(11) has no driver
Warning (10034): Output port "d" at ads7846a.vhd(11) has no driver
Warning (10034): Output port "ydout[11]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[10]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[9]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[8]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[7]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[6]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[5]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[4]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[3]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[2]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[1]" at ads7846a.vhd(13) has no driver
Warning (10034): Output port "ydout[0]" at ads7846a.vhd(13) has no driver
Info (10041): Inferred latch for "wait_flag" at ads7846a.vhd(44)
Info (10041): Inferred latch for "pen" at ads7846a.vhd(44)
Info: Elaborating entity "fenpin" for hierarchy "fenpin:inst1"
Warning (14130): Reduced register "ADS7846a:inst|write_control[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ADS7846a:inst|write_control[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ADS7846a:inst|write_control[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ADS7846a:inst|write_control[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ADS7846a:inst|write_control[0]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "ADS7846a:inst|write_control[4]" merged to single register "ADS7846a:inst|write_control[7]"
Info: State machine "|Block1|ADS7846a:inst|state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|Block1|ADS7846a:inst|state"
Info: Encoding result for state machine "|Block1|ADS7846a:inst|state"
Info: Completed encoding using 5 state bits
Info: Encoded state bit "ADS7846a:inst|state.wait_300ms"
Info: Encoded state bit "ADS7846a:inst|state.read_bit"
Info: Encoded state bit "ADS7846a:inst|state.write_bit"
Info: Encoded state bit "ADS7846a:inst|state.control"
Info: Encoded state bit "ADS7846a:inst|state.reset"
Info: State "|Block1|ADS7846a:inst|state.reset" uses code string "00000"
Info: State "|Block1|ADS7846a:inst|state.control" uses code string "00011"
Info: State "|Block1|ADS7846a:inst|state.write_bit" uses code string "00101"
Info: State "|Block1|ADS7846a:inst|state.read_bit" uses code string "01001"
Info: State "|Block1|ADS7846a:inst|state.wait_300ms" uses code string "10001"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "a" stuck at GND
Warning (13410): Pin "B" stuck at GND
Warning (13410): Pin "C" stuck at GND
Warning (13410): Pin "D" stuck at GND
Warning (13410): Pin "ydout[11]" stuck at GND
Warning (13410): Pin "ydout[10]" stuck at GND
Warning (13410): Pin "ydout[9]" stuck at GND
Warning (13410): Pin "ydout[8]" stuck at GND
Warning (13410): Pin "ydout[7]" stuck at GND
Warning (13410): Pin "ydout[6]" stuck at GND
Warning (13410): Pin "ydout[5]" stuck at GND
Warning (13410): Pin "ydout[4]" stuck at GND
Warning (13410): Pin "ydout[3]" stuck at GND
Warning (13410): Pin "ydout[2]" stuck at GND
Warning (13410): Pin "ydout[1]" stuck at GND
Warning (13410): Pin "ydout[0]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "busy"
Info: Implemented 152 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 31 output pins
Info: Implemented 117 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 46 warnings
Info: Allocated 161 megabytes of memory during processing
Info: Processing ended: Wed Mar 18 22:33:32 2009
Info: Elapsed time: 00:00:03
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