fenpin.vhd.bak

四线电阻式触摸屏

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fenpin is
port( clk50mhz:in std_logic;
      clk2mhz:buffer std_logic;
	  clk1khz:out std_logic);
end;
architecture behav of fenpin is
begin

process(clk50mhz)--2mhz时钟信号
variable cnt1:integer range 0 to 25:=0; 
begin
if rising_edge(clk50mhz) then cnt1:=cnt1+1;
 if cnt1<12 then clk2mhz<='0';
  elsif cnt1<25 then clk2mhz<='1';
   else cnt1:=0;clk2mhz<='0';
 end if;
end if;
end process;

process(clk2mhz)
variable cnt2:integer range 0 to 2000:=0;
begin
if rising_edge(clk2mhz) then cnt2:=cnt2+1;
 if cnt2<1000 then clk1khz<='0';
  elsif cnt2<2000 then clk1khz<='1';
   else cnt2:=0;clk1khz<='0';
 end if;
end if;
end process;
end;