lpc32x0.s

nxp 3250 的nandflash的bootloader

;//           <0=> Active LOW chip select
;//           <1=> Active HIGH chip select
;//         <o0.3> PM: Page mode enable
;//         <o0.0..1> MW: Memory width
;//           <0=> 8 bit
;//           <1=> 16 bit
;//           <2=> 32 bit
;//       </h>
EMCStaConfig3_Val   EQU 0x00000002

;//       <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen3)
;//         <i> Selects the delay from CS3 to write enable
;//         <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;//           <i> The delay is in HCLK cycles
;//       </h>
EMCStaWaitWen3_Val  EQU 0x00000000

;//       <h> Static Memory Output Enable Delay Register (EMCStaticWaitOen3)
;//         <i> Selects the delay from CS3 or address change, whichever is later, to output enable
;//         <o.0..3> WAITOEN: Wait output enable <0-15>
;//           <i> The delay is in HCLK cycles
;//       </h>
EMCStaWaitOen3_Val  EQU 0x00000000
                                      
;//       <h> Static Memory Read Delay Register (EMCStaticWaitRd3)
;//         <i> Selects the delay from CS3 to a read access
;//         <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;//           <i> The delay is in HCLK cycles
;//       </h>
EMCStaWaitRd3_Val   EQU 0x0000001F

;//       <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3)
;//         <i> Selects the delay for asynchronous page mode sequential accesses for CS3
;//         <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;//           <i> The delay is in HCLK cycles
;//       </h>
EMCStaWaitPage3_Val EQU 0x0000001F

;//       <h> Static Memory Write Delay Register (EMCStaticWaitWr3)
;//         <i> Selects the delay from CS3 to a write access
;//         <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;//           <i> The delay is in HCLK cycles
;//       </h>
EMCStaWaitWr3_Val   EQU 0x0000001F

;//       <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn3)
;//         <i> Selects the number of bus turnaround cycles for CS3
;//         <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;//           <i> The delay is in HCLK cycles
;//       </h>
EMCStaWaitTurn3_Val EQU 0x0000000F

;//     </e> End of Static Setup for Static CS3 Area

;//     <h> Static Memory Extended Wait Register (EMCStaticExtendedWait)
;//       <i> Time long static memory read and write transfers
;//       <o.0..9> EXTENDEDWAIT: Extended wait time out <0-1023>
;//         <i> The delay is in (16 * HCLK) cycles
;//     </h>
EMCStaExtWait_Val   EQU 0x00000000

;//   </e> End of Static Setup

;// </e> End of EMC Setup


;----------------------- NAND Flash Definitions --------------------------------

; NAND Flash Controller (NANDC) User Interface
; Single-level NAND flash controller definitions
FLASHCLK_CTRL_OFS   EQU     0xC8        ; NAND Configuration Reg  Address Offset
                                        
SLC_BASE            EQU     0x20020000  ; SLC NAND Controller     Base Address
                                        ; SLC NAND Flash Registers
SLC_DATA_OFS        EQU     0x00        ; Data           Register Address Offset
SLC_ADDR_OFS        EQU     0x04        ; Address        Register Address Offset
SLC_CMD_OFS         EQU     0x08        ; Command        Register Address Offset
SLC_STOP_OFS        EQU     0x0C        ; STOP           Register Address Offset
SLC_CTRL_OFS        EQU     0x10        ; Control        Register Address Offset
SLC_CFG_OFS         EQU     0x14        ; Configuration  Register Address Offset
SLC_STAT_OFS        EQU     0x18        ; Status         Register Address Offset
SLC_INT_STAT_OFS    EQU     0x1C        ; Interrupt Status    Reg Address Offset
SLC_IEN_OFS         EQU     0x20        ; Interrupt Enable    Reg Address Offset
SLC_ISR_OFS         EQU     0x24        ; Interrupt Set       Reg Address Offset
SLC_ICR_OFS         EQU     0x28        ; Interrupt Clear     Reg Address Offset
SLC_TAC_OFS         EQU     0x2C        ; Read Timing Arc Cfg Reg Address Offset
SLC_TC_OFS          EQU     0x30        ; Transfer Count Register Address Offset
SLC_ECC_OFS         EQU     0x34        ; Parity Bits    Register Address Offset
SLC_DMA_DATA_OFS    EQU     0x38        ; DMA DATA       Register Address Offset

; Multi-level NAND flash controller definitions
MLC_DATA_BASE       EQU     0x200A8000  ; MLC Data Buffer         Base Address
MLC_BASE            EQU     0x200B8000  ; MLC NAND Controller     Base Address
                                        ; MLC NAND Flash Registers
MLC_CMD_OFS         EQU     0x00        ; Command        Register Address Offset
MLC_ADDR_OFS        EQU     0x04        ; Address        Register Address Offset
MLC_ECC_ENC_REG_OFS EQU     0x08        ; ECC Encode     Register Address Offset
MLC_ECC_DEC_REG_OFS EQU     0x0C        ; ECC Decode     Register Address Offset
MLC_ECC_AUTO_ENC_REG_OFS EQU 0x10       ; ECC Auto Encode     Reg Address Offset
MLC_ECC_AUTO_DEC_REG_OFS EQU 0x14       ; ECC Auto Decode     Reg Address Offset
MLC_RPR_OFS         EQU     0x18        ; Read Parity    Register Address Offset
MLC_WPR_OFS         EQU     0x1C        ; Write Parity   Register Address Offset
MLC_RUBP_OFS        EQU     0x20        ; Reset User Buf Ptr  Reg Address Offset
MLC_ROBP_OFS        EQU     0x24        ; Reset Overhead Buf Ptr  Address Offset
MLC_SW_WP_ADD_LOW_OFS EQU   0x28        ; Sw Wr Protect Low   Reg Address Offset
MLC_SW_WP_ADD_HIG_OFS EQU   0x2C        ; Sw Wr Protect High  Reg Address Offset
MLC_ICR_OFS         EQU     0x30        ; Configuration  Register Address Offset
MLC_TIME_REG_OFS    EQU     0x34        ; Timing         Register Address Offset
MLC_IRQ_MR_OFS      EQU     0x38        ; Interrupt Mask Register Address Offset
MLC_IRQ_SR_OFS      EQU     0x3C        ; Interrupt Status    Reg Address Offset
MLC_LOCK_PR_OFS     EQU     0x44        ; Lock Protection     Reg Address Offset
MLC_ISR_OFS         EQU     0x48        ; Status         Register Address Offset
MLC_CEH_OFS         EQU     0x4C        ; Chip-Enable Host Ctrl R Address Offset


; NAND Flash Commands
NAND_CMD_READ0      EQU     0x00        ; Read mode (1) command
NAND_CMD_READ1      EQU     0x01        ; Read mode (2) command
NAND_CMD_PAGEPROG   EQU     0x10        ; Auto program command
NAND_CMD_READSTART  EQU     0x30        ; Read start command
NAND_CMD_READ2      EQU     0x50        ; Read mode (3) command
NAND_CMD_ERASE1ST   EQU     0x60        ; Auto block erase 1-st command
NAND_CMD_STATUS     EQU     0x70        ; Status read (1) command
NAND_CMD_STATUS_MULTI EQU   0x71        ; Status read (2) command
NAND_CMD_SDIN       EQU     0x80        ; Serial data input command
NAND_CMD_READID     EQU     0x90        ; ID read (1) command
NAND_CMD_ERASE2ND   EQU     0xD0        ; Auto block erase 2-nd command
NAND_CMD_RESET      EQU     0xFF        ; Reset command

; NAND Constants
MLC_LOCK_Val        EQU     0xA25E      ; Unlocking               Constant

;// <e> NAND Flash Controller Configuration (NANDC)
NANDC_SETUP    EQU     0

;//   <h> NAND Clock Control Register (FLASHCLK_CTRL)
;//     <o0.5>   NAND Flash Controller Interrupt
;//                   <0=> SLC NAND Flash controller interrupt enabled
;//                   <1=> MLC NAND Flash controller interrupt enabled
;//                   <i>  Default: SLC NAND Flash controller interrupt enabled
;//     <o0.4>   NAND_DMA_REQ on NAND_RnB (only for MLC)
;//                   <0=> Disabled
;//                   <1=> Enabled
;//                   <i>  Default: Disabled
;//     <o0.3>   NAND_DMA_REQ on NAND_INT (only for MLC)
;//                   <0=> Disabled
;//                   <1=> Enabled
;//                   <i>  Default: Disabled
;//     <o0.2>   SLC/MLC Select
;//                   <0=> Multi-level (MLC) NAND Flash controller
;//                   <1=> Single-level (LLC) NAND Flash controller
;//                   <i>  Default: Multi-level (MLC) NAND Flash controller
;//     <o0.1>   MLC NAND Flash Clock Enable
;//                   <0=> Disabled
;//                   <1=> Enabled
;//                   <i>  Default: Enabled
;//     <o0.0>   SLC NAND Flash Clock Enable
;//                   <0=> Disabled
;//                   <1=> Enabled
;//                   <i>  Default: Enabled
;//   </h>
FLASHCLK_CTRL_Val  EQU  0x00000002

;//   <h> MLC NAND Flash Chip-Enable Host Control Register (MLC_CEH)
;//     <o0.0>   nCE Assert
;//                   <0=> Force nCE assert
;//                   <1=> Normal nCE operation (nCE controlled by controller)
;//                   <i>  Default: Force nCE assert
;//   </h>
MLC_CEH_Val        EQU  0x00000000

;//   <h> MLC NAND Controller Configuration Register (MLC_ICR)
;//     <o0.3>   Software Write Protection
;//                   <0=> Disabled
;//                   <1=> Enabled
;//                   <i>  Default: Disabled
;//     <o0.2>   Block Size
;//                   <0=> Small block flash device ( 512 + 16 bytes page)
;//                   <1=> Large block flash device (2048 + 64 bytes page)
;//                   <i>  Default: Small block flash device ( 512 + 16 bytes page)
;//     <o0.1>   NAND Flash Address Word Count
;//                   <0=> 3 address cycles
;//                   <1=> 4 address cycles
;//                   <i>  Default: 3 address cycles
;//     <o0.0>   NAND Flash I/O Bus Width
;//                   <0=> 8-bit bus width
;//                   <1=> 16-bit bus width (Not supported)
;//                   <i>  Default: 8-bit bus width
;//   </h>
MLC_ICR_Val        EQU  0x00000000

;// </e> NAND Flash Controller Configuration (NANDC)


;----------------------- Vector Floating-Point Definitions ---------------------

; Constants
VFP_EN_BIT      EQU     (1<<30)         ; VFP Enable Bit


;----------------------- Cache Definitions -------------------------------------

; Constants
ICACHE_EN_BIT   EQU     (1<<12)         ; Instruction Cache Enable Bit

;// <e> Instruction Cache Enable
;// </e>
ICACHE_SETUP    EQU     0


;----------------------- CODE --------------------------------------------------

                PRESERVE8


; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.

                AREA    RESET, CODE, READONLY
                ARM

                IF      :DEF:SIZE_INT_INFO
                IMPORT  ||Image$$ER_IROM1$$RO$$Length||
                IMPORT  ||Image$$RW_IRAM1$$RW$$Length||
                ELIF    :DEF:SIZE_EXT_INFO
                IMPORT  ||Image$$ER_ROM1$$RO$$Length||
                IMPORT  ||Image$$RW_RAM1$$RW$$Length||
                ENDIF

; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.

Vectors         LDR     PC,Reset_Addr         
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
                ; Reserved vector is used for image size information
                IF      :DEF:SIZE_INT_INFO
                  DCD   ||Image$$ER_IROM1$$RO$$Length||+\
                        ||Image$$RW_IRAM1$$RW$$Length||
                ELIF    :DEF:SIZE_EXT_INFO
                  DCD   ||Image$$ER_ROM1$$RO$$Length||+\
                        ||Image$$RW_RAM1$$RW$$Length||
                ELSE
                  NOP
                ENDIF
                LDR     PC,IRQ_Addr     
                LDR     PC,FIQ_Addr

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0               ; Reserved Address
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler

Undef_Handler   B       Undef_Handler
SWI_Handler     B       SWI_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
IRQ_Handler     B       IRQ_Handler
FIQ_Handler     B       FIQ_Handler


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler   


; Clock Setup ------------------------------------------------------------------

                IF      CLOCK_SETUP != 0