lpc32x0.s

nxp 3250 的nandflash的bootloader

EMCAHBControl4_OFS  EQU     0x480       ; AHB port 4 Control Reg  Address Offset
EMCAHBStatus4_OFS   EQU     0x484       ; AHB port 4 Status  Reg  Address Offset
EMCAHBTimeOut4_OFS  EQU     0x488       ; AHB port 4 Timeout Reg  Address Offset

SDRAM0_MODE_REG     EQU     0x80018000  ; SDRAM0 Mode Register     Address
SDRAM0_EXT_MODE_REG EQU     0x8102C000  ; SDRAM0 Extended Mode Reg Address
SDRAM1_MODE_REG     EQU     0xA0018000  ; SDRAM1 Mode Register     Address
SDRAM1_EXT_MODE_REG EQU     0xA102C000  ; SDRAM1 Extended Mode Reg Address

; Constants
NORMAL_CMD          EQU     (0x0 << 7)  ; NORMAL        Command
MODE_CMD            EQU     (0x1 << 7)  ; MODE          Command
PALL_CMD            EQU     (0x2 << 7)  ; Precharge All Command
NOP_CMD             EQU     (0x3 << 7)  ; NOP           Command
REFSH_MODE          EQU     (0x1 << 2)  ; Self-refresh mode

;//     External Memory Controller Setup (EMC) ---------------------------------
;// <e> External Memory Controller Setup (EMC)
EMC_SETUP           EQU 1

;//   <h> EMC Control Register (EMCControl)
;//     <i> Controls operation of the memory controller
;//     <o0.2> L: SDRAM Low-power mode enable
;//     <o0.0> E: SDRAM Controller enable
;//   </h>
EMCControl_Val      EQU 0x00000001

;//   <h> EMC Configuration Register (EMCConfig)
;//     <i> Configures operation of the memory controller
;//     <o0.0> Endian mode
;//       <0=> Little-endian
;//       <1=> Big-endian
;//   </h>
EMCConfig_Val       EQU 0x00000000

;//       Dynamic Memory Interface Setup ---------------------------------------
;//   <e> Dynamic Memory Interface Setup
EMC_DYNAMIC_SETUP   EQU 1

;//     <h> SDRAM Clock Control Register (SDRAMCLK_CTRL)
;//       <o0.22> SDRAM_PIN_SPEED3: Slew rate on the pin SDRAM pin CLK
;//                   <0=> Fast
;//                   <1=> Slow
;//                   <i>  Default: Fast
;//       <o0.21> SDRAM_PIN_SPEED2: Slew rate on the pins SDRAM pads A[14:0], CKE, CS_N, RAS_N, CAS_N, WR_N
;//                   <0=> Fast
;//                   <1=> Slow
;//                   <i>  Default: Fast
;//       <o0.20> SDRAM_PIN_SPEED1: Slew rate on the pins SDRAM pads D[31:0], DQM[3:0]
;//                   <0=> Fast
;//                   <1=> Slow
;//                   <i>  Default: Fast
;//       <o0.19> SW_DDR_RESET: Reset SDRAM Controller when writing from 0 to 1
;//                   <0=> No Reset
;//                   <1=> Reset Active
;//                   <i>  Default: No Reset
;//       <o0.14..18> HCLKDELAY_DELAY: Delay of the HCLKDELAY input from the HCLK <0-31>
;//                   <i>  Delay = value programmed * 0.25ns
;//                   <i>  Default: 0
;//       <o0.13> Delay circuitry Adder status
;//                   <0=> No overflow or sign bit
;//                   <1=> Last calibration produced overflow or negative number
;//       <o0.10..12> Sensitivity factor for DDR SDRAM calibration <0-7>
;//                   <i>  Number of bits to shift error value
;//                   <i>  Default: 0
;//       <o0.9> CAL_DELAY: Delay settings for DDR SDRAM
;//                   <0=> Un-calibrated
;//                   <1=> Calibrated
;//                   <i>  Default: Un-calibrated
;//       <o0.8> SW_DDR_CAL: Perform DDR calibration
;//                   <0=> No manual DDR delay calibration
;//                   <1=> Perform a DDR delay calibration
;//                   <i>  Default: No manual DDR delay calibration
;//       <o0.7> RTC_TICK_EN: Automatic DDR delay calibration
;//                   <0=> No
;//                   <1=> Yes, on each RTC TICK
;//                   <i>  Default: No
;//       <o0.2..6> DDR_DQSIN_DELAY: Delay of the DQS input from the DDR SDRAM device
;//                   <0-15>
;//                   <i>  Delay = value programmed * 0.25ns
;//                   <i>  Default: 0
;//       <o0.1> DDR_SEL: Pin multiplexing selection
;//                   <0=> SDR SDRAM used
;//                   <1=> DDR SDRAM used
;//                   <i>  Default: SDR SDRAM used
;//       <o0.0> Clock enable
;//                   <0=> SDRAM HCLK and inverted HCLK enabled
;//                   <1=> All clocks to SDRAM block disabled
;//                   <i>  Default: SDRAM HCLK and inverted HCLK enabled
;//     </h>
SDRAMCLK_CTRL_Val  EQU  0x0001C000

;//     <h> Dynamic Memory Refresh Timer Register (EMCDynamicRefresh)
;//       <i> Configures dynamic memory refresh operation
;//       <o0.0..10> REFRESH: Refresh timer <0x000-0x7FF>
;//         <i> 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS
;//     </h>
EMCDynRefresh_Val   EQU 0x00000032

;//     <h> Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
;//       <i> Configures the dynamic memory read strategy
;//       <o0.12> DRP: DDR-SDRAM read data capture polarity
;//         <0=> Data captured on the negative edge of HCLK
;//         <1=> Data captured on the positive edge of HCLK
;//       <o0.8..9> DRD: DDR-SDRAM read data strategy
;//         <0=> Clock out delayed strategy
;//         <1=> Command delayed strategy
;//         <2=> Command delayed strategy plus one clock cycle
;//         <3=> Command delayed strategy plus two clock cycles
;//       <o0.4> SRP: SDR-SDRAM read data capture polarity
;//         <0=> Data captured on the negative edge of HCLK
;//         <1=> Data captured on the positive edge of HCLK
;//       <o0.0..1> SRD: SDR-SDRAM read data strategy
;//         <0=> Clock out delayed strategy
;//         <1=> Command delayed strategy
;//         <2=> Command delayed strategy plus one clock cycle
;//         <3=> Command delayed strategy plus two clock cycles
;//     </h>
EMCDynReadCfg_Val   EQU 0x00000011

;//     <h> Dynamic Memory Timings
;//       <i> All delays are in clock cycles
;//       <h> Dynamic Memory Precharge Command Period Register (EMCDynamictRP)
;//         <o0.0..3> tRP: Precharge command period <1-16> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tRP
;//       </h>
;//       <h> Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS)
;//         <o1.0..3> tRAS: Active to precharge command period <1-16> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tRAS
;//       </h>
;//       <h> Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX)
;//         <o2.0..3> tSREX: Self-refresh exit time <1-16> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tSREX 
;//           <i> for devices without this parameter you use the same value as tXSR
;//       </h>
;//       <h> Dynamic Memory Write Recovery Time Register (EMCDynamictWR)
;//         <o3.0..3> tWR: Write recovery time <1-16> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL
;//       </h>
;//       <h> Dynamic Memory Active to Active Command Period Register (EMCDynamictRC)
;//         <o4.0..4> tRC: Active to active command period <1-32> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tRC
;//       </h>
;//       <h> Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC)
;//         <o5.0..4> tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tRFC or tRC
;//       </h>
;//       <h> Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR)
;//         <o6.0..8> tXSR: Exit self-refresh to active command time <1-256> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tXSR
;//       </h>
;//       <h> Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD)
;//         <o7.0..3> tRRD: Active bank A to active bank B latency <1-16> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tRRD
;//       </h>
;//       <h> Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD)
;//         <o8.0..3> tMRD: Load mode register to active command time <1-16> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tMRD or tRSA
;//       </h>
;//       <h> Dynamic Memory Last Data In to Read Command Time (EMCDynamictCDLR)
;//         <o9.0..3> tCDLR: Last data in to read command time <1-16> <#-1>
;//           <i> This value is normally found in SDRAM data sheets as tCDLR
;//       </h>
;//     </h>
EMCDynRP_Val        EQU 0x00000001
EMCDynRAS_Val       EQU 0x00000004
EMCDynSREX_Val      EQU 0x00000008
EMCDynWR_Val        EQU 0x00000001
EMCDynRC_Val        EQU 0x00000007
EMCDynRFC_Val       EQU 0x00000008
EMCDynXSR_Val       EQU 0x00000008
EMCDynRRD_Val       EQU 0x00000002
EMCDynMRD_Val       EQU 0x00000002
EMCDynCDLR_Val      EQU 0x00000001

;//     <e> Configure External Bus Behaviour for Dynamic CS0 Area
EMC_DYNCS0_SETUP    EQU 1

;//       <h> Dynamic Memory Configuration Register (EMCDynamicConfig0)
;//         <i> Defines the configuration information for the dynamic memory CS0
;//         <o0.20> P: Write protect enable
;//         <o0.14> AM 14: External bus data width
;//           <0=> 16 bit
;//           <1=> 32 bit
;//         <o0.12..13> AM 13..12: External bus memory type
;//           <0=> High-performance
;//           <1=> Low-power SDRAM
;//         <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column)
;//           <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9
;//           <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8
;//           <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9
;//           <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8
;//           <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10
;//           <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9
;//           <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10
;//           <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9
;//           <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11
;//           <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10
;//         <o0.3..4> MD: Memory device
;//           <0=> SDR SDRAM
;//           <2=> Low-power SDR SDRAM
;//           <4=> DDR SDRAM
;//           <6=> Low-power DDR SDRAM
;//       </h>
EMCDynConfig0_Val   EQU 0x00005682

;//       <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0)
;//         <i> Controls the RAS and CAS latencies for the dynamic memory CS0
;//         <o0.7..10 > CAS: CAS latency
;//           <1=> 0.5 clock cycle
;//           <2=> 1 clock cycles
;//           <3=> 1.5 clock cycle
;//           <4=> 2 clock cycles
;//           <5=> 2.5 clock cycle
;//           <6=> 3 clock cycles
;//           <7=> 3.5 clock cycle
;//           <8=> 4 clock cycles
;//           <9=> 4.5 clock cycle
;//           <10=> 5 clock cycles
;//           <11=> 5.5 clock cycle
;//           <12=> 6 clock cycles
;//           <13=> 6.5 clock cycle
;//           <14=> 7 clock cycles
;//           <15=> 7.5 clock cycle
;//         <o0.0..3> RAS: RAS latency (active to read/write delay, in clock cycles) <1-15>
;//       </h>
EMCDynRasCas0_Val   EQU 0x00000303

;//       <e> Configure AHB0 Interface for SDRAM Controller
;//         <h> SDRAM Controller AHB Control Register (EMCAHBControl0)
;//           <o1.0..1> E: AHB Port Buffer Enable
;//         </h>
;//         <h> SDRAM Controller AHB Timeout Register (EMCAHBTime0)
;//           <o2.0..9> AHBTIMEOUT: AHB timeout <0-511>
;//             <i> 0 = timeout disabled, 1-511 value: number of AHB cycles
;//         </h>
;//       </e> Configure AHB0 Interface for SDRAM Controller
EMC_AHB0_SETUP      EQU 1
EMCAHBControl0_Val  EQU 0x00000001
EMCAHBTimeOut0_Val  EQU 0x00000064

;//       <e> Configure AHB2 Interface for SDRAM Controller
;//         <h> SDRAM Controller AHB Control Register (EMCAHBControl2)
;//           <o1.0..1> E: AHB Port Buffer Enable
;//         </h>
;//         <h> SDRAM Controller AHB Timeout Register (EMCAHBTime2)
;//           <o2.0..9> AHBTIMEOUT: AHB timeout <0-511>
;//             <i> 0 = timeout disabled, 1-511 value: number of AHB cycles
;//         </h>
;//       </e> Configure AHB2 Interface for SDRAM Controller
EMC_AHB2_SETUP      EQU 1
EMCAHBControl2_Val  EQU 0x00000001
EMCAHBTimeOut2_Val  EQU 0x00000190

;//       <e> Configure AHB3 Interface for SDRAM Controller
;//         <h> SDRAM Controller AHB Control Register (EMCAHBControl3)
;//           <o1.0..1> E: AHB Port Buffer Enable
;//         </h>
;//         <h> SDRAM Controller AHB Timeout Register (EMCAHBTime3)
;//           <o2.0..9> AHBTIMEOUT: AHB timeout <0-511>
;//             <i> 0 = timeout disabled, 1-511 value: number of AHB cycles
;//         </h>
;//       </e> Configure AHB3 Interface for SDRAM Controller
EMC_AHB3_SETUP      EQU 1
EMCAHBControl3_Val  EQU 0x00000001
EMCAHBTimeOut3_Val  EQU 0x00000190

;//       <e> Configure AHB4 Interface for SDRAM Controller
;//         <h> SDRAM Controller AHB Control Register (EMCAHBControl4)
;//           <o1.0..1> E: AHB Port Buffer Enable
;//         </h>
;//         <h> SDRAM Controller AHB Timeout Register (EMCAHBTime4)
;//           <o2.0..9> AHBTIMEOUT: AHB timeout <0-511>
;//             <i> 0 = timeout disabled, 1-511 value: number of AHB cycles
;//         </h>
;//       </e> Configure AHB4 Interface for SDRAM Controller
EMC_AHB4_SETUP      EQU 1
EMCAHBControl4_Val  EQU 0x00000001