📄 lpc32x0.s
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;/*****************************************************************************/
;/* LPC32x0.S: Startup file for Philips LPC32x0 device series */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
;/*
; * The LPC32x0.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * EMC_NO_INIT: when set, the external memory controller is not initialized
; * in startup (if 2-nd level bootloader is used this should
; * set as bootloader already initializes SDRAM).
; *
; * EMC_DYNAMIC_NO_INIT: when set, the dynamic memory interface of the
; * external memory controller is not initialized in startup
; *
; * EMC_STATIC_NO_INIT: when set, the static memory interface of the
; * external memory controller is not initialized in startup
; *
; * NAND_NO_INIT: when set, the NAND Flash controller is not initialized in
; * startup (if 2-nd level bootloader is used this should
; * be set as bootloader already initializes NAND Flash
; * controller).
; *
; * RAM_INTVEC: when set, the startup code copies exception vectors
; * from on-chip Flash to on-chip RAM.
; *
; * REMAP: when set, the startup code remaps exception vectors from
; * on-chip RAM to address 0.
; *
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;----------------------- Memory Definitions ------------------------------------
; Internal Memory Base Addresses
IRAM_BASE EQU 0x08000000
IROM_BASE EQU 0x0C000000
; External Memory Base Addresses
DYN_MEM0_BASE EQU 0x80000000
DYN_MEM1_BASE EQU 0xA0000000
STA_MEM0_BASE EQU 0xE0000000
STA_MEM1_BASE EQU 0xE1000000
STA_MEM2_BASE EQU 0xE2000000
STA_MEM3_BASE EQU 0xE3000000
; System Control User Interface
SYSTEM_BASE EQU 0x40004000 ; System Control Base Address
BOOT_MAP_OFS EQU 0x14 ; Boot Map Control Reg Address Offset
SDRAMCLK_CTRL_OFS EQU 0x68 ; SDRAM Clock Control Reg Address Offset
DDR_LAP_NOM_OFS EQU 0x6C ; DDR DQS Nominal Value Address Offset
DDR_LAP_COUNT_OFS EQU 0x70 ; DDR Ring Osc Counter Address Offset
DDR_CAL_DELAY_OFS EQU 0x74 ; DDR DQS Calibrate Value Address Offset
; Constants
REMAP_BIT EQU (1<<0) ; Remap RAM to 0
;----------------------- Stack and Heap Definitions ----------------------------
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000020
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000000
USR_Stack_Size EQU 0x00000000
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
;----------------------- Clock Definitions -------------------------------------
; Clock User Interface
PWR_CTRL_OFS EQU 0x44 ; Power Control Register Address Offset
OSC_CTRL_OFS EQU 0x4C ; Main Oscilator Ctrl Reg Address Offset
SYSCLK_CTRL_OFS EQU 0x50 ; SYSCLK Control Register Address Offset
PLL397_CTRL_OFS EQU 0x48 ; PLL397 Control Register Address Offset
HCLKPLL_CTRL_OFS EQU 0x58 ; ARM and HCLK Ctrl Reg Address Offset
HCLKDIV_CTRL_OFS EQU 0x40 ; HCLK Divider Settings Address Offset
; Constants
NORMAL_RUN_BIT EQU (1<<2) ; Run mode control bit
SYSCLK_PLL_BIT EQU (1<<1) ; PLL397 used for system clock bit
PLL_LOCK_BIT EQU (1<<0) ; PLL locked bit
HCLKPLL_PD_BIT EQU (1<<16) ; HCLK PLL power down mode bit
;// <e> Clock Configuration
CLOCK_SETUP EQU 1
;// <h> Main Oscillator Control Register (OSC_CTRL)
;// <e0.0> Main Oscillator Disable
;// </e>
;// </h>
OSC_CTRL_Val EQU 0x00000000
;// <h> SYSCLK Control Register (SYSCLK_CTRL)
;// <o0.2..11> Bad Phase Length Before Clock Switching Trigger <0x000-0x3FF>
;// <o0.1> Oscillator Switch
;// <0=> Switch to main oscillator
;// <1=> Switch to 13MHz clock source (PLL397 output)
;// </h>
SYSCLK_CTRL_Val EQU 0x00000140
;// <h> PLL397 Control Register (PLL397_CTRL)
;// <o0.1> PLL397 Operational Control
;// <0=> PLL397 is running
;// <1=> PLL397 is stopped and is in low power mode
;// </h>
PLL397_CTRL_Val EQU 0x00000000
;// <h> HCLK PLL Control Register (HCLKPLL_CTRL)
;// <i> Example for 208MHz PLL from 13MHz oscillator
;// <i> settings:
;// <i> - PLL Power Down: PLL in operating mode
;// <i> - Bypass Control: CCO clock is sent to post-divider
;// <i> - Direct Output Control: CCO clock is the direct output of the PLL
;// <i> - Feedback Divider Path Control: don't care
;// <i> - PLL Post-divider Settings (P): don't care
;// <i> - PLL Pre-divider Settings (N): 1
;// <i> - PLL Feedback Divider (M): 16
;// <o0.16> PLL Power Down
;// <0=> PLL in power down mode
;// <1=> PLL in operating mode
;// <o0.15> Bypass Control
;// <0=> CCO clock is sent to post-divider
;// <1=> PLL input bypasses the CCO
;// <o0.14> Direct Output Control
;// <0=> The output of the post-divider is output of the PLL
;// <1=> CCO clock is the direct output of the PLL
;// <o0.13> Feedback Divider Path Control
;// <0=> Clocked by CCO clock
;// <1=> Clocked by PLL_CLKOUT
;// <o0.11..12> PLL Post-divider Settings (P)
;// <0=> / 2 (P=1)
;// <1=> / 4 (P=2)
;// <2=> / 8 (P=4)
;// <3=> / 16 (P=8)
;// <o0.9..10> PLL Pre-divider Settings (N)
;// <0=> 1
;// <1=> 2
;// <2=> 3
;// <3=> 4
;// <o0.1..8> PLL Feedback Divider (M)
;// <1-256><#-1>
;// </h>
HCLKPLL_CTRL_Val EQU 0x0001401E
;// <h> HCLK Divider Control Register (HCLKDIV_CTRL)
;// <o0.7..8> DDRAM_CLK Control
;// <0=> Stopped
;// <1=> Nominal speed
;// <2=> Half speed
;// <o0.2..6> PERIPH_CLK Divider Control <1-32><#-1>
;// <i> PERIPH_CLK = ARM PLL clock / value
;// <o0.0..1> HCLK Divider Control
;// <0=> HCLK = ARM PLL clock
;// <1=> HCLK = ARM PLL clock / 2
;// <2=> HCLK = ARM PLL clock / 4
;// </h>
HCLKDIV_CTRL_Val EQU 0x0000003D
;// </e> Clock Configuration
;----------------------- EMC Definitions ---------------------------------------
; External Memory Controller (EMC) User Interface
EMC_BASE EQU 0x31080000 ; EMC Controller Base Address
EMCControl_OFS EQU 0x00 ; Memory Controller Contr Address Offset
EMCStatus_OFS EQU 0x04 ; EMC Status Address Offset
EMCConfig_OFS EQU 0x08 ; Mem Controller Oper Cfg Address Offset
EMCDynControl_OFS EQU 0x20 ; Dynamic Mem Control Reg Address Offset
EMCDynRefresh_OFS EQU 0x24 ; Dynamic Mem Refresh Reg Address Offset
EMCDynReadCfg_OFS EQU 0x28 ; Dynamic Mem Read Config Address Offset
EMCDynRP_OFS EQU 0x30 ; Precharge Cmd Period Address Offset
EMCDynRAS_OFS EQU 0x34 ; Active to Prchg Period Address Offset
EMCDynSREX_OFS EQU 0x38 ; Self-refresh Exit Time Address Offset
EMCDynWR_OFS EQU 0x44 ; Write Recovery Time Address Offset
EMCDynRC_OFS EQU 0x48 ; Act to Act Cmd Period Address Offset
EMCDynRFC_OFS EQU 0x4C ; Auto-refresh Period Address Offset
EMCDynXSR_OFS EQU 0x50 ; Exit Selfref to Act Cmd Address Offset
EMCDynRRD_OFS EQU 0x54 ; Active bank A to B Address Offset
EMCDynMRD_OFS EQU 0x58 ; Load Mode to Act Cmd Address Offset
EMCDynCDLR_OFS EQU 0x5C ; Last data into Read Cmd Address Offset
EMCStaExtWait_OFS EQU 0x80 ; Static Mem Extend Wait Address Offset
EMCDynConfig0_OFS EQU 0x100 ; SDRAM0 Config Info Address Offset
EMCDynRasCas0_OFS EQU 0x104 ; RAS0 and CAS0 Latencies Address Offset
EMCDynConfig1_OFS EQU 0x120 ; SDRAM1 Config Info Address Offset
EMCDynRasCas1_OFS EQU 0x124 ; RAS1 and CAS1 Latencies Address Offset
EMCStaConfig0_OFS EQU 0x200 ; CS0 Memory Config Address Offset
EMCStaWaitWen0_OFS EQU 0x204 ; CS0 to Wr Enable Delay Address Offset
EMCStaWaitOen0_OFS EQU 0x208 ; CS0 to Out Enable Delay Address Offset
EMCStaWaitRd0_OFS EQU 0x20C ; CS0 to Rd Access Delay Address Offset
EMCStaWaitPage0_OFS EQU 0x210 ; CS0 Seq Access Delay Address Offset
EMCStaWaitWr0_OFS EQU 0x214 ; CS0 to Wr Access Delay Address Offset
EMCStaWaitTurn0_OFS EQU 0x218 ; CS0 Turnaround Cycles Address Offset
EMCStaConfig1_OFS EQU 0x220 ; CS1 Memory Config Address Offset
EMCStaWaitWen1_OFS EQU 0x224 ; CS1 to Wr Enable Delay Address Offset
EMCStaWaitOen1_OFS EQU 0x228 ; CS1 to Out Enable Delay Address Offset
EMCStaWaitRd1_OFS EQU 0x22C ; CS1 to Rd Access Delay Address Offset
EMCStaWaitPage1_OFS EQU 0x230 ; CS1 Seq Access Delay Address Offset
EMCStaWaitWr1_OFS EQU 0x234 ; CS1 to Wr Access Delay Address Offset
EMCStaWaitTurn1_OFS EQU 0x238 ; CS1 Turnaround Cycles Address Offset
EMCStaConfig2_OFS EQU 0x240 ; CS2 Memory Config Address Offset
EMCStaWaitWen2_OFS EQU 0x244 ; CS2 to Wr Enable Delay Address Offset
EMCStaWaitOen2_OFS EQU 0x248 ; CS2 to Out Enable Delay Address Offset
EMCStaWaitRd2_OFS EQU 0x24C ; CS2 to Rd Access Delay Address Offset
EMCStaWaitPage2_OFS EQU 0x250 ; CS2 Seq Access Delay Address Offset
EMCStaWaitWr2_OFS EQU 0x254 ; CS2 to Wr Access Delay Address Offset
EMCStaWaitTurn2_OFS EQU 0x258 ; CS2 Turnaround Cycles Address Offset
EMCStaConfig3_OFS EQU 0x260 ; CS3 Memory Config Address Offset
EMCStaWaitWen3_OFS EQU 0x264 ; CS3 to Wr Enable Delay Address Offset
EMCStaWaitOen3_OFS EQU 0x268 ; CS3 to Out Enable Delay Address Offset
EMCStaWaitRd3_OFS EQU 0x26C ; CS3 to Rd Access Delay Address Offset
EMCStaWaitPage3_OFS EQU 0x270 ; CS3 Seq Access Delay Address Offset
EMCStaWaitWr3_OFS EQU 0x274 ; CS3 to Wr Access Delay Address Offset
EMCStaWaitTurn3_OFS EQU 0x278 ; CS3 Turnaround Cycles Address Offset
EMCAHBControl0_OFS EQU 0x400 ; AHB port 0 Control Reg Address Offset
EMCAHBStatus0_OFS EQU 0x404 ; AHB port 0 Status Reg Address Offset
EMCAHBTimeOut0_OFS EQU 0x408 ; AHB port 0 Timeout Reg Address Offset
EMCAHBControl2_OFS EQU 0x440 ; AHB port 2 Control Reg Address Offset
EMCAHBStatus2_OFS EQU 0x444 ; AHB port 2 Status Reg Address Offset
EMCAHBTimeOut2_OFS EQU 0x448 ; AHB port 2 Timeout Reg Address Offset
EMCAHBControl3_OFS EQU 0x460 ; AHB port 3 Control Reg Address Offset
EMCAHBStatus3_OFS EQU 0x464 ; AHB port 3 Status Reg Address Offset
EMCAHBTimeOut3_OFS EQU 0x468 ; AHB port 3 Timeout Reg Address Offset
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