sam9263.s

atmel 9263的boottloader

;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o2.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o2.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o2.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 3 (MATRIX_SCFG3)
;//       <o3.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o3.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o3.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o3.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 4 (MATRIX_SCFG4)
;//       <o4.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o4.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o4.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o4.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 5 (MATRIX_SCFG5)
;//       <o5.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o5.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o5.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o5.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 6 (MATRIX_SCFG6)
;//       <o6.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o6.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o6.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o6.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 7 (MATRIX_SCFG7)
;//       <o7.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o7.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o7.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o7.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//   </h>
MATRIX_SCFG0_Val EQU    0x00000010
MATRIX_SCFG1_Val EQU    0x00000010
MATRIX_SCFG2_Val EQU    0x00000010
MATRIX_SCFG3_Val EQU    0x00000010
MATRIX_SCFG4_Val EQU    0x00000010
MATRIX_SCFG5_Val EQU    0x00000010
MATRIX_SCFG6_Val EQU    0x00000010
MATRIX_SCFG7_Val EQU    0x00000010

;//   <h> Bus Matrix Priority Registers For Slaves
;//     <h> Bus Matrix Priority Register A For Slaves 0 (MATRIX_PRAS0)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o0.0..1>   M0PR: Master 0 Priority
;//       <o0.4..5>   M1PR: Master 1 Priority
;//       <o0.8..9>   M2PR: Master 2 Priority
;//       <o0.12..13> M3PR: Master 3 Priority
;//       <o0.16..17> M4PR: Master 4 Priority
;//       <o0.20..21> M5PR: Master 5 Priority
;//       <o0.24..25> M6PR: Master 6 Priority
;//       <o0.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 0 (MATRIX_PRBS0)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o1.0..1>   M8PR: Master 8 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register A For Slaves 1 (MATRIX_PRAS1)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o2.0..1>   M0PR: Master 0 Priority
;//       <o2.4..5>   M1PR: Master 1 Priority
;//       <o2.8..9>   M2PR: Master 2 Priority
;//       <o2.12..13> M3PR: Master 3 Priority
;//       <o2.16..17> M4PR: Master 4 Priority
;//       <o2.20..21> M5PR: Master 5 Priority
;//       <o2.24..25> M6PR: Master 6 Priority
;//       <o2.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 1 (MATRIX_PRBS1)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o3.0..1>   M8PR: Master 8 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register A For Slaves 2 (MATRIX_PRAS2)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o4.0..1>   M0PR: Master 0 Priority
;//       <o4.4..5>   M1PR: Master 1 Priority
;//       <o4.8..9>   M2PR: Master 2 Priority
;//       <o4.12..13> M3PR: Master 3 Priority
;//       <o4.16..17> M4PR: Master 4 Priority
;//       <o4.20..21> M5PR: Master 5 Priority
;//       <o4.24..25> M6PR: Master 6 Priority
;//       <o4.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 2 (MATRIX_PRBS2)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o5.0..1>   M8PR: Master 8 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register A For Slaves 3 (MATRIX_PRAS3)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o6.0..1>   M0PR: Master 0 Priority
;//       <o6.4..5>   M1PR: Master 1 Priority
;//       <o6.8..9>   M2PR: Master 2 Priority
;//       <o6.12..13> M3PR: Master 3 Priority
;//       <o6.16..17> M4PR: Master 4 Priority
;//       <o6.20..21> M5PR: Master 5 Priority
;//       <o6.24..25> M6PR: Master 6 Priority
;//       <o6.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 3 (MATRIX_PRBS3)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o7.0..1>   M8PR: Master 8 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register A For Slaves 4 (MATRIX_PRAS4)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o8.0..1>   M0PR: Master 0 Priority
;//       <o8.4..5>   M1PR: Master 1 Priority
;//       <o8.8..9>   M2PR: Master 2 Priority
;//       <o8.12..13> M3PR: Master 3 Priority
;//       <o8.16..17> M4PR: Master 4 Priority
;//       <o8.20..21> M5PR: Master 5 Priority
;//       <o8.24..25> M6PR: Master 6 Priority
;//       <o8.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 4 (MATRIX_PRBS4)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o9.0..1>   M8PR: Master 8 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register A For Slaves 5 (MATRIX_PRAS5)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o10.0..1>   M0PR: Master 0 Priority
;//       <o10.4..5>   M1PR: Master 1 Priority
;//       <o10.8..9>   M2PR: Master 2 Priority
;//       <o10.12..13> M3PR: Master 3 Priority
;//       <o10.16..17> M4PR: Master 4 Priority
;//       <o10.20..21> M5PR: Master 5 Priority
;//       <o10.24..25> M6PR: Master 6 Priority
;//       <o10.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 5 (MATRIX_PRBS5)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o11.0..1>   M8PR: Master 8 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register A For Slaves 6 (MATRIX_PRAS6)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o12.0..1>   M0PR: Master 0 Priority
;//       <o12.4..5>   M1PR: Master 1 Priority
;//       <o12.8..9>   M2PR: Master 2 Priority
;//       <o12.12..13> M3PR: Master 3 Priority
;//       <o12.16..17> M4PR: Master 4 Priority
;//       <o12.20..21> M5PR: Master 5 Priority
;//       <o12.24..25> M6PR: Master 6 Priority
;//       <o12.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 6 (MATRIX_PRBS6)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o13.0..1>   M8PR: Master 8 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register A For Slaves 7 (MATRIX_PRAS7)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o14.0..1>   M0PR: Master 0 Priority
;//       <o14.4..5>   M1PR: Master 1 Priority
;//       <o14.8..9>   M2PR: Master 2 Priority
;//       <o14.12..13> M3PR: Master 3 Priority
;//       <o14.16..17> M4PR: Master 4 Priority
;//       <o14.20..21> M5PR: Master 5 Priority
;//       <o14.24..25> M6PR: Master 6 Priority
;//       <o14.28..29> M7PR: Master 7 Priority
;//     </h>
;//     <h> Bus Matrix Priority Register B For Slaves 7 (MATRIX_PRBS7)
;//       <i> Fixed priority of Master 8 for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o15.0..1>   M8PR: Master 8 Priority
;//     </h>
;//   </h>
MATRIX_PRAS0_Val EQU    0x00000000
MATRIX_PRBS0_Val EQU    0x00000000
MATRIX_PRAS1_Val EQU    0x00000000
MATRIX_PRBS1_Val EQU    0x00000000
MATRIX_PRAS2_Val EQU    0x00000000
MATRIX_PRBS2_Val EQU    0x00000000
MATRIX_PRAS3_Val EQU    0x00000000
MATRIX_PRBS3_Val EQU    0x00000000
MATRIX_PRAS4_Val EQU    0x00000000
MATRIX_PRBS4_Val EQU    0x00000000
MATRIX_PRAS5_Val EQU    0x00000000
MATRIX_PRBS5_Val EQU    0x00000000
MATRIX_PRAS6_Val EQU    0x00000000
MATRIX_PRBS6_Val EQU    0x00000000
MATRIX_PRAS7_Val EQU    0x00000000
MATRIX_PRBS7_Val EQU    0x00000000