sam9263.s

atmel 9263的boottloader

;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//     <o6.8..9>   MDIV: Master Clock Division
;//                   <0=> Processor Clock = Master Clock
;//                   <1=> Processor Clock = Master Clock / 2
;//                   <2=> Processor Clock = Master Clock / 3
;//                   <3=> Processor Clock = Master Clock / 4
;//   </h>
;//
;//   <h> Programmable Clock Register 0 (PMC_PCK0)
;//     <o7.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o7.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> Clock        <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 1 (PMC_PCK1)
;//     <o8.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o8.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 2 (PMC_PCK2)
;//     <o9.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o9.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 3 (PMC_PCK3)
;//     <o10.0..1>  CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o10.2..4>  PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;// </e>
PMC_SETUP       EQU     1
PMC_SCER_Val    EQU     0x00000001
PMC_PCER_Val    EQU     0x0000001C
CKGR_MOR_Val    EQU     0x0000FF01
CKGR_PLLAR_Val  EQU     0x206DBF09
CKGR_PLLBR_Val  EQU     0x00000000
PMC_MCKR_Val    EQU     0x00000006
PMC_PCK0_Val    EQU     0x00000000
PMC_PCK1_Val    EQU     0x00000000
PMC_PCK2_Val    EQU     0x00000000
PMC_PCK3_Val    EQU     0x00000000


;----------------------- MATRIX Definitions ------------------------------------

; Bus Matrix (MATRIX) User Interface
; |- Chip Configuration (CCFG) User Interface
MATRIX_BASE      EQU    0xFFFFEC00      ; Bus Matrix              Base Address
MATRIX_MCFG0_OFS EQU    0x00            ; Master Config Reg 0     Address Offset
MATRIX_MCFG1_OFS EQU    0x04            ; Master Config Reg 1     Address Offset
MATRIX_MCFG2_OFS EQU    0x08            ; Master Config Reg 2     Address Offset
MATRIX_MCFG3_OFS EQU    0x0C            ; Master Config Reg 3     Address Offset
MATRIX_MCFG4_OFS EQU    0x10            ; Master Config Reg 4     Address Offset
MATRIX_MCFG5_OFS EQU    0x14            ; Master Config Reg 5     Address Offset
MATRIX_MCFG6_OFS EQU    0x18            ; Master Config Reg 6     Address Offset
MATRIX_MCFG7_OFS EQU    0x1C            ; Master Config Reg 7     Address Offset
MATRIX_MCFG8_OFS EQU    0x20            ; Master Config Reg 8     Address Offset
MATRIX_SCFG0_OFS EQU    0x40            ; Slave Config Reg 0      Address Offset
MATRIX_SCFG1_OFS EQU    0x44            ; Slave Config Reg 1      Address Offset
MATRIX_SCFG2_OFS EQU    0x48            ; Slave Config Reg 2      Address Offset
MATRIX_SCFG3_OFS EQU    0x4C            ; Slave Config Reg 3      Address Offset
MATRIX_SCFG4_OFS EQU    0x50            ; Slave Config Reg 4      Address Offset
MATRIX_SCFG5_OFS EQU    0x54            ; Slave Config Reg 5      Address Offset
MATRIX_SCFG6_OFS EQU    0x58            ; Slave Config Reg 6      Address Offset
MATRIX_SCFG7_OFS EQU    0x5C            ; Slave Config Reg 7      Address Offset
MATRIX_PRAS0_OFS EQU    0x80            ; Priority A for Slave 0  Address Offset
MATRIX_PRBS0_OFS EQU    0x84            ; Priority B for Slave 0  Address Offset
MATRIX_PRAS1_OFS EQU    0x88            ; Priority A for Slave 1  Address Offset
MATRIX_PRBS1_OFS EQU    0x8C            ; Priority B for Slave 1  Address Offset
MATRIX_PRAS2_OFS EQU    0x90            ; Priority A for Slave 2  Address Offset
MATRIX_PRBS2_OFS EQU    0x94            ; Priority B for Slave 2  Address Offset
MATRIX_PRAS3_OFS EQU    0x98            ; Priority A for Slave 3  Address Offset
MATRIX_PRBS3_OFS EQU    0x9C            ; Priority B for Slave 3  Address Offset
MATRIX_PRAS4_OFS EQU    0xA0            ; Priority A for Slave 4  Address Offset
MATRIX_PRBS4_OFS EQU    0xA4            ; Priority B for Slave 4  Address Offset
MATRIX_PRAS5_OFS EQU    0xA8            ; Priority A for Slave 5  Address Offset
MATRIX_PRBS5_OFS EQU    0xAC            ; Priority B for Slave 5  Address Offset
MATRIX_PRAS6_OFS EQU    0xB0            ; Priority A for Slave 6  Address Offset
MATRIX_PRBS6_OFS EQU    0xB4            ; Priority B for Slave 6  Address Offset
MATRIX_PRAS7_OFS EQU    0xB8            ; Priority A for Slave 7  Address Offset
MATRIX_PRBS7_OFS EQU    0xBC            ; Priority B for Slave 7  Address Offset
MATRIX_MRCR_OFS  EQU    0x100           ; Master Remap Control R  Address Offset
MATRIX_TCMR_OFS  EQU    0x114           ; TCM Configuration Reg   Address Offset
EBI0_CSA_OFS     EQU    0x120           ; EBI Chip Select 0 Asign Address Offset
EBI1_CSA_OFS     EQU    0x124           ; EBI Chip Select 1 Asign Address Offset

; Constants
EBI0_CS0_ADDRESS EQU    0x10000000      ; Start of EBI 0 memory addressed by CS0
EBI0_CS1_ADDRESS EQU    0x20000000      ; Start of EBI 0 memory addressed by CS1
EBI0_CS2_ADDRESS EQU    0x30000000      ; Start of EBI 0 memory addressed by CS2
EBI0_CS3_ADDRESS EQU    0x40000000      ; Start of EBI 0 memory addressed by CS3
EBI0_CS4_ADDRESS EQU    0x50000000      ; Start of EBI 0 memory addressed by CS4
EBI0_CS5_ADDRESS EQU    0x60000000      ; Start of EBI 0 memory addressed by CS5
EBI1_CS0_ADDRESS EQU    0x70000000      ; Start of EBI 1 memory addressed by CS0
EBI1_CS1_ADDRESS EQU    0x80000000      ; Start of EBI 1 memory addressed by CS1
EBI1_CS2_ADDRESS EQU    0x90000000      ; Start of EBI 1 memory addressed by CS2

;// <e> Bus Matrix (MATRIX)
MATRIX_SETUP    EQU     0

;//   <h> Bus Matrix Master Configuration Registers
;//     <h>  Bus Matrix Master Configuration Registers 0 (MATRIX_MCFG0)
;//       <o0.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 1 (MATRIX_MCFG1)
;//       <o1.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 2 (MATRIX_MCFG2)
;//       <o2.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 3 (MATRIX_MCFG3)
;//       <o3.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 4 (MATRIX_MCFG4)
;//       <o4.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 5 (MATRIX_MCFG5)
;//       <o5.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 6 (MATRIX_MCFG6)
;//       <o6.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 7 (MATRIX_MCFG7)
;//       <o7.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//     <h>  Bus Matrix Master Configuration Registers 8 (MATRIX_MCFG8)
;//       <o8.0..2> ULBT: Undefined Length Burst Type 
;//                   <0=> Infinite Length Burst
;//                   <1=> Single Access
;//                   <2=> Four Beat Burst
;//                   <3=> Eight Beat Burst
;//                   <4=> Sixteen Beat Burst
;//     </h>
;//   </h>
MATRIX_MCFG0_Val EQU    0x00000000
MATRIX_MCFG1_Val EQU    0x00000002
MATRIX_MCFG2_Val EQU    0x00000002
MATRIX_MCFG3_Val EQU    0x00000002
MATRIX_MCFG4_Val EQU    0x00000002
MATRIX_MCFG5_Val EQU    0x00000002
MATRIX_MCFG6_Val EQU    0x00000002
MATRIX_MCFG7_Val EQU    0x00000002
MATRIX_MCFG8_Val EQU    0x00000002

;//   <h> Bus Matrix Slave Configuration Registers
;//     <h> Bus Master Slave Configuration Regsiter 0 (MATRIX_SCFG0)
;//       <o0.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o0.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o0.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o0.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 1 (MATRIX_SCFG1)
;//       <o1.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o1.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o1.18..21> FIXED_DEFMSTR: Fixed Index of Default Master <0-15>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o1.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 2 (MATRIX_SCFG2)
;//       <o2.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst