📄 sam9263.s
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;/*****************************************************************************/
;/* SAM9263.S: Startup file for Atmel AT91SAM9263 device series */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
;/*
; * The SAM9263.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * SIZE_INT_INFO: size of program image is coded instead of Reserved vector
; * at address 0x14, if code is located in Internal RAM.
; *
; * SIZE_EXT_INFO: size of program image is coded instead of Reserved vector
; * at address 0x14, if code is located in External SDRAM.
; *
; * REMAP: when set the startup code remaps exception vectors from
; * on-chip RAM to address 0.
; *
; * RAM_INTVEC: when set the startup code copies exception vectors
; * from Image Load Address to on-chip RAM.
; *
; * NO_SDRAM_INIT: when set the SDRAM controller is not initialized in startup
; * and it is used when SDRAM controller is initialized from debugger
; * enviroment (using the debug script).
; *
; * NO_PMC_INIT: when set the Power Management Controller and system clock
; * are not initialized in startup and it is used when PLL is initialized from
; * debugger enviroment (using the debug script).
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
; Internal Memory Base Addresses
ITCM_BASE EQU 0x00100000
DTCM_BASE EQU 0x00200000
IRAM_BASE EQU 0x00300000
IROM_BASE EQU 0x00400000
IRAM0_BASE EQU 0x00500000
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000008
USR_Stack_Size EQU 0x00000040
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
;----------------------- PIOs Definitions --------------------------------------
; Parallel Input/Output Controller (PIO) User Interface
PIOA_BASE EQU 0xFFFFF200 ; PIO A Base Address
PIOB_BASE EQU 0xFFFFF400 ; PIO B Base Address
PIOC_BASE EQU 0xFFFFF600 ; PIO C Base Address
PIOD_BASE EQU 0xFFFFF800 ; PIO D Base Address
PIOE_BASE EQU 0xFFFFFA00 ; PIO E Base Address
PIO_PER_OFS EQU 0x00 ; PIO Enable Register Address Offset
PIO_PDR_OFS EQU 0x04 ; PIO Disable Register Address Offset
PIO_OER_OFS EQU 0x10 ; PIO Output Enable Reg Address Offset
PIO_ODR_OFS EQU 0x14 ; PIO Output Disable Reg Address Offset
PIO_MDER_OFS EQU 0x50 ; PIO Multi-Driver En Reg Address Offset
PIO_MDDR_OFS EQU 0x54 ; PIO Multi-Driver Ds Reg Address Offset
PIO_PUDR_OFS EQU 0x60 ; PIO Pull-up Disable Reg Address Offset
PIO_PUER_OFS EQU 0x64 ; PIO Pull-up Enable Reg Address Offset
PIO_ASR_OFS EQU 0x70 ; PIO Periph A Select Reg Address Offset
PIO_BSR_OFS EQU 0x74 ; PIO Periph B Select Reg Address Offset
;----------------------- Power Management Controller (PMC) Definitions ---------
; Power Management Controller (PMC) definitions
PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address
PMC_SCER_OFS EQU 0x00 ; Sys Clk Enable Reg Address Offset
PMC_SCDR_OFS EQU 0x04 ; Sys Clk Disable Reg Address Offset
PMC_SCSR_OFS EQU 0x08 ; Sys Clk Status Reg Address Offset
PMC_PCER_OFS EQU 0x10 ; Periph Clk Enable Reg Address Offset
PMC_PCDR_OFS EQU 0x14 ; Periph Clk Disable Reg Address Offset
PMC_PCSR_OFS EQU 0x18 ; Periph Clk Status Reg Address Offset
CKGR_MOR_OFS EQU 0x20 ; Main Oscillator Reg Address Offset
CKGR_MCFR_OFS EQU 0x24 ; Main Clock Freq Reg Address Offset
CKGR_PLLAR_OFS EQU 0x28 ; PLLA Reg Address Offset
CKGR_PLLBR_OFS EQU 0x2C ; PLLA Reg Address Offset
PMC_MCKR_OFS EQU 0x30 ; Master Clock Reg Address Offset
PMC_PCK0_OFS EQU 0x40 ; Programmable Clk 0 Reg Address Offset
PMC_PCK1_OFS EQU 0x44 ; Programmable Clk 1 Reg Address Offset
PMC_PCK2_OFS EQU 0x48 ; Programmable Clk 2 Reg Address Offset
PMC_PCK3_OFS EQU 0x4C ; Programmable Clk 3 Reg Address Offset
PMC_IER_OFS EQU 0x60 ; Interrupt Enable Reg Address Offset
PMC_IDR_OFS EQU 0x64 ; Interrupt Disable Reg Address Offset
PMC_SR_OFS EQU 0x68 ; Status Register Address Offset
PMC_IMR_OFS EQU 0x6C ; Interrupt Mask Reg Address Offset
PMC_PLLICPR_OFS EQU 0x80 ; Charge Pump Current Reg Address Offset
; Bit constants
PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable
PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier
PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable
PMC_LOCKA EQU (1<<1) ; PLL A Lock Status
PMC_LOCKB EQU (1<<2) ; PLL A Lock Status
PMC_MCKRDY EQU (1<<3) ; Master Clock Status
;// <e> Power Management Controller (PMC)
;// <h> System Clock Enable Register (PMC_SCER)
;// <o1.0> PCK: Processor Clock Enable
;// <o1.6> UHP: USB Host Port Clock Enable
;// <o1.7> UDP: USB Device Port Clock Enable
;// <o1.8> PCK0: Programmable Clock 0 Output Enable
;// <o1.9> PCK1: Programmable Clock 1 Output Enable
;// <o1.10> PCK2: Programmable Clock 2 Output Enable
;// <o1.11> PCK3: Programmable Clock 3 Output Enable
;// </h>
;//
;// <h> Peripheral Clock Enable Register (PMC_PCER)
;// <o2.2> PID2: Parallel IO Controller A Enable
;// <o2.3> PID3: Parallel IO Controller B Enable
;// <o2.4> PID4: Parallel IO Controller C, D, E Enable
;// <o2.7> PID7: USART0 Enable
;// <o2.8> PID8: USART1 Enable
;// <o2.9> PID9: USART2 Enable
;// <o2.10> PID10: Multimedia Card Interface 0 Enable
;// <o2.11> PID11: Multimedia Card Interface 1 Enable
;// <o2.12> PID12: CAN Controller Enable
;// <o2.13> PID13: Two-Wire Interface Enable
;// <o2.14> PID14: Serial Peripheral Interface 0 Enable
;// <o2.15> PID15: Serial Peripheral Interface 1 Enable
;// <o2.16> PID16: Serial Synchronous Controller 0 Enable
;// <o2.17> PID17: Serial Synchronous Controller 1 Enable
;// <o2.18> PID18: AC97 Controller Enable
;// <o2.19> PID19: Timer Counter 0, 1, 2 Enable
;// <o2.20> PID20: PWM Controller Enable
;// <o2.21> PID21: Ethernet MAC Enable
;// <o2.23> PID23: 2D Graphic Engine Enable
;// <o2.24> PID24: USB Device Port Enable
;// <o2.25> PID25: Image Sensor Interface Enable
;// <o2.26> PID26: LCD Controller Enable
;// <o2.27> PID27: DMA Controller Enable
;// <o2.29> PID29: USB Host Port Enable
;// <o2.30> PID30: Advanced Interrupt Controller (IRQ0) Enable
;// <o2.31> PID31: Advanced Interrupt Controller (IRQ1) Enable
;// </h>
;//
;// <h> Main Oscillator Register (CKGR_MOR)
;// <o3.0> MOSCEN: Main Oscillator Enable
;// <o3.8..15> OSCOUNT: Main Oscillator Startup Time <0-255>
;// </h>
;//
;// <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR)
;// <i> PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1)
;// <i> Example: XTAL = 16.367660 MHz, DIVA = 9, MULA = 109 => PLLA = 200.049178 MHz
;// <o4.0..7> DIVA: PLL Divider A <0-255>
;// <i> 0 - Divider output is 0
;// <i> 1 - Divider is bypassed
;// <i> 2 .. 255 - Divider output is the Main Clock divided by DIVA
;// <o4.8..13> PLLACOUNT: PLL A Counter <0-63>
;// <i> Number of Slow Clocks before the LOCKA bit is set in
;// <i> PMC_SR after CKGR_PLLAR is written
;// <o4.14..15> OUTA: PLL A Clock Frequency Range
;// <0=> 80 .. 160MHz <1=> Reserved
;// <2=> 150 .. 240MHz <3=> Reserved
;// <o4.16..26> MULA: PLL A Multiplier <0-2047>
;// <i> 0 - The PLL A is deactivated
;// <i> 1 .. 2047 - The PLL A Clock frequency is the PLL a input
;// <i> frequency multiplied by MULA + 1
;// </h>
;//
;// <h> Clock Generator Phase Locked Loop B Register (CKGR_PLLBR)
;// <i> PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1)
;// <o5.0..7> DIVB: PLL Divider B <0-255>
;// <i> 0 - Divider output is 0
;// <i> 1 - Divider is bypassed
;// <i> 2 .. 255 - Divider output is the Main Clock divided by DIVB
;// <o5.8..13> PLLBCOUNT: PLL B Counter <0-63>
;// <i> Number of Slow Clocks before the LOCKB bit is set in
;// <i> PMC_SR after CKGR_PLLBR is written
;// <o5.14..15> OUTB: PLL B Clock Frequency Range
;// <0=> 80 .. 160MHz <1=> Reserved
;// <2=> 150 .. 240MHz <3=> Reserved
;// <o5.16..26> MULB: PLL B Multiplier <0-2047>
;// <i> 0 - The PLL B is deactivated
;// <i> 1 .. 2047 - The PLL B Clock frequency is the PLL a input
;// <i> frequency multiplied by MULB + 1
;// <o5.28> USB_96M: Divider by 2 Enable
;// <i> 0 - USB ports = PLL B Clock, PLL B Clock must be 48MHz
;// <i> 1 - USB ports = PLL B Clock / 2, PLL B Clock must be 96MHz
;// </h>
;//
;// <h> Master Clock Register (CKGR_MCKR)
;// <o6.0..1> CSS: Master Clock Selection
;// <0=> Slow Clock
;// <1=> Main Clock
;// <2=> PLL A Clock
;// <3=> PLL B Clock
;// <o6.2..4> PRES: Master Clock Prescaler
;// <0=> Clock <1=> Clock / 2
;// <2=> Clock / 4 <3=> Clock / 8
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