os_cpu_a.s

ucos ii 2.83的完整版,包含接口程序

;********************************************************************************************************
;                                               uC/OS-II
;                                         The Real-Time Kernel
;
;                               (c) Copyright 1992-2004, Micrium, Weston, FL
;                                          All Rights Reserved
;
;                                               ARM7 Port
;                                            IAR C Compiler
;
; File : OS_CPU_A.ASM
; By   : Jean J. Labrosse
;********************************************************************************************************
		AREA  |subr|, CODE, READONLY
		
		INCLUDE 	/at91sam7x256/include/arm7tdmi/arm.inc
		INCLUDE		/at91sam7x256/include/AT91SAM7X256.inc


        IMPORT  OSRunning                        ; External references
        IMPORT  OSTCBCur
        IMPORT  OSTCBHighRdy
        IMPORT  OSPrioCur
        IMPORT  OSPrioHighRdy
        IMPORT  OSIntCtxSwFlag

        IMPORT  OSIntEnter
        IMPORT  OSIntExit

        IMPORT  OSTaskSwHook
        IMPORT	OSTimeTick
        IMPORT	Uart_Debug_ISR        


        EXPORT  OSStartHighRdy                   ; Functions declared in this file
        EXPORT 	ARMDisableInt
		EXPORT 	ARMEnableInt
        EXPORT  OSCtxSw
        EXPORT  TC_OS_IntCtxSw
        EXPORT  OS_CPU_SR_Save
        EXPORT  OS_CPU_SR_Restore
        EXPORT 	TC_OSTickISR
        EXPORT	PIT_OS_IntCtxSw
        EXPORT 	PIT_OSTickISR
		EXPORT	ARMCoreDisableIntExt
		EXPORT	ARMCoreRestoreIntStatus

NO_INT  EQU     0xC0                             ; Mask used to disable interrupts (Both FIR and IRQ)
;*********************************************************************************************************
;                                   CRITICAL SECTION METHOD 3 FUNCTIONS
;
; Description: Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
;              would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
;              disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to 
;              disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
;              into the CPU's status register.
;
; Prototypes :     OS_CPU_SR  OS_CPU_SR_Save(void);
;                  void       OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
;
;
; Note(s)    : 1) These functions are used in general like this:
;
;                 void Task (void *p_arg)
;                 {
;                 #if OS_CRITICAL_METHOD == 3          /* Allocate storage for CPU status register */
;                     OS_CPU_SR  cpu_sr;
;                 #endif
;
;                          :
;                          :
;                     OS_ENTER_CRITICAL();             /* cpu_sr = OS_CPU_SaveSR();                */
;                          :
;                          :
;                     OS_EXIT_CRITICAL();              /* OS_CPU_RestoreSR(cpu_sr);                */
;                          :
;                          :
;                 }
;
;              2) OS_CPU_SaveSR() is implemented as recommended by Atmels application note:
;
;                    "Disabling Interrupts at Processor Level"
;*********************************************************************************************************
OS_CPU_SR_Save
        MRS     R0,CPSR                     ; Set IRQ and FIQ bits in CPSR to disable all interrupts
        ORR     R1,R0,#NO_INT
        MSR     CPSR_c,R1
        MRS     R1,CPSR                     ; Confirm that CPSR contains the proper interrupt disable flags
        AND     R1,R1,#NO_INT
        CMP     R1,#NO_INT
        BNE     OS_CPU_SR_Save              ; Not properly disabled (try again)
        MOV     PC,LR                       ; Disabled, return the original CPSR contents in R0


OS_CPU_SR_Restore
        MSR     CPSR_c,R0
        MOV     PC,LR
        
ARMDisableInt             	    
		MRS     R12, CPSR           		; get current CPU mode
  		ORR     R12, R12, #I_BIT    		; set the interrupt disable mode bit
  		MSR     CPSR_c, R12         
  		BX		LR                  


ARMEnableInt
  		MRS 	R12, CPSR             		; move current processor status into reg 12  
  		BIC 	R12, R12, #I_BIT      		; clear the interrupt disable bit
  		MSR 	CPSR_c, R12           
  		BX		LR         

;*********************************************************************************************************
;                                          START MULTITASKING
;                                       void OSStartHighRdy(void)
;
; Note : OSStartHighRdy() MUST:
;           a) Call OSTaskSwHook() then,
;           b) Set OSRunning to TRUE,
;           c) Switch to the highest priority task.
;*********************************************************************************************************
OSStartHighRdy  

        MSR     CPSR_cxsf,#0xD3         	; Switch to SVC mode with IRQ and FIQ disabled

        BL      OSTaskSwHook            	; OSTaskSwHook();

        LDR     R4,=OSRunning         		; OSRunning = TRUE
        MOV     R5,#1
        STRB    R5,[R4]

        LDR     R4,=OSTCBHighRdy      		; Get highest priority task TCB address
        LDR     R4,[R4]                 	; get stack pointer
        LDR     SP,[R4]                 	; switch to the new stack

        LDMFD   SP!,{R4}                	; pop new tasks SPSR
        MSR     SPSR_cxsf,R4
        LDMFD   SP!,{R4}                	; pop new tasks CPSR
        MSR     CPSR_cxsf,R4
        LDMFD   SP!,{R0-R12,LR,PC}      	; pop new tasks R0-R12,LR & PC

;*********************************************************************************************************
;                                PERFORM A CONTEXT SWITCH (From task level)
;
; Note(s): Upon entry: 
;              OSTCBCur      points to the OS_TCB of the task to suspend
;              OSTCBHighRdy  points to the OS_TCB of the task to resume
;*********************************************************************************************************

OSCtxSw
        STMFD   SP!,{LR}                	; push PC (lr should be pushed in place of PC)
        STMFD   SP!,{R0-R12,LR}         	; push LR & register file
        MRS     R4,CPSR
        STMFD   SP!,{R4}                	; push current PSR
        MRS     R4,SPSR
        STMFD   SP!,{R4}                	; push current SPSR

        LDR     R4,=OSTCBCur          		; Get current task's OS_TCB address
        LDR     R5,[R4]
        STR     SP,[R5]                 	; store sp in preempted tasks's TCB

        BL      OSTaskSwHook            	; OSTaskSwHook();

        LDR     R4,=OSPrioCur         		; OSPrioCur = OSPrioHighRdy
        LDR     R5,=OSPrioHighRdy
        LDRB    R6,[R5]
        STRB    R6,[R4]
        
        LDR     R4,=OSTCBCur         	 	; Get the current tasks OS_TCB address
        LDR     R6,=OSTCBHighRdy      		; Get highest priority tasks OS_TCB address
        LDR     R6,[R6]
        LDR     SP,[R6]                 	; get new tasks stack pointer

        STR     R6,[R4]                 	; OSTCBCur = OSTCBHighRdy

        LDMFD   SP!,{R4}                	; pop new tasks SPSR
        MSR     SPSR_cxsf,R4
        LDMFD   SP!,{R4}                	; pop new tasks PSR
        MSR     CPSR_cxsf,r4
        LDMFD   SP!,{R0-R12,LR,PC}      	; pop new tasks R0-R12,LR & PC

;*********************************************************************************************************
;                                  INTERRUPT LEVEL CONTEXT SWITCH
;
; Description:  This code performs a context switch if a higher priority task has been made ready-to-run
;               during an ISR.
;*********************************************************************************************************
TC_OS_IntCtxSw
        LDR     R0,=OSIntCtxSwFlag    		; OSIntCtxSwFlag = FALSE
        MOV     R1,#0
        STR     R1,[R0]

        LDMFD   SP!,{R0-R3,R12,LR}      	; Clean up IRQ stack
        STMFD   SP!,{R0-R3}             	; We will use R0-R3 as temporary registers
        MOV     R1,SP
        ADD     SP,SP,#16
        SUB     R2,LR,#4

        MRS     R3,SPSR                 	; Disable interrupts for when we go back to SVC mode
        ORR     R0,R3,#NO_INT
        BIC		R0,R0,#0x00000020			; 这一句很关键，是整个系统稳定运行的重要因素
        MSR     SPSR_c,R0

        LDR     R0,=.+8                 	; Switch back to SVC mode (Code below, current location + 2 instructions)