controller.c

开源代码

		break;
	case 1066:
		switch ((mchcfg >> 4)&7) {
			case 5:	dramratio = 3.0f/2.0f; break;
			case 6:	dramratio = 2.0f; break;
		}
		break;
}

	// Compute RAM Frequency
	fsb = ((extclock / 1000) / coef);
	dramclock = fsb * dramratio;

	// Print DRAM Freq
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB (only if ECC is not enabled) */
	cprint(LINE_CPU+5, col +1, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;

}


static void poll_fsb_5400(void) {

	double dramclock, dramratio, fsb;
	unsigned long ambase_low, ambase_high, ddrfrq;
	float coef = getP4PMmultiplier();

	/* Find dramratio */
	pci_conf_read( 0, 16, 0, 0x48, 4, &ambase_low);
	ambase_low &= 0xFFFE0000;
	pci_conf_read( 0, 16, 0, 0x4C, 4, &ambase_high);
	ambase_high &= 0xFF;
	pci_conf_read( 0, 16, 1, 0x56, 1, &ddrfrq);
  ddrfrq &= 7;
  dramratio = 1;

	switch (ddrfrq) {
			case 0:	
			case 1:	
			case 4:					
				dramratio = 1.0; 
				break;
			case 2:	
				dramratio = 5.0f/4.0f; 
				break;
			case 3:	
			case 7:	
				dramratio = 4.0f/5.0f; 
				break;
		}


	// Compute RAM Frequency
	fsb = ((extclock / 1000) / coef);
	dramclock = fsb * dramratio;

	// Print DRAM Freq
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB (only if ECC is not enabled) */
	cprint(LINE_CPU+5, col +1, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;

}


static void poll_fsb_nf4ie(void) {

	double dramclock, dramratio, fsb;
	float mratio, nratio;
	unsigned long reg74, reg60;
	float coef = getP4PMmultiplier();
	
	/* Find dramratio */
	pci_conf_read(0, 0, 2, 0x74, 2, &reg74);
	pci_conf_read(0, 0, 2, 0x60, 4, &reg60);
	mratio = reg74 & 0xF;
	nratio = (reg74 >> 4) & 0xF;

	// If M or N = 0, then M or N = 16
	if (mratio == 0) { mratio = 16; }
	if (nratio == 0) { nratio = 16; }
	
	// Check if synchro or pseudo-synchro mode
	if((reg60 >> 22) & 1) {
		dramratio = 1;
	} else {
		dramratio = nratio / mratio;
	}

	/* Compute RAM Frequency */
	fsb = ((extclock /1000) / coef);
	dramclock = fsb * dramratio;

	/* Print DRAM Freq */
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB  */
	cprint(LINE_CPU+5, col, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;
	
}

static void poll_fsb_i875(void) {

	double dramclock, dramratio, fsb;
	unsigned long mchcfg, smfs;
	float coef = getP4PMmultiplier();

	/* Find dramratio */
	pci_conf_read(0, 0, 0, 0xC6, 2, &mchcfg);
	smfs = (mchcfg >> 10)&3;
	dramratio = 1;

	if ((mchcfg&3) == 3) { dramratio = 1; }
	if ((mchcfg&3) == 2) {
		if (smfs == 2) { dramratio = 1; }
		if (smfs == 1) { dramratio = 1.25; }
		if (smfs == 0) { dramratio = 1.5; }
	}
	if ((mchcfg&3) == 1) {
		if (smfs == 2) { dramratio = 0.6666666666; }
		if (smfs == 1) { dramratio = 0.8; }
		if (smfs == 0) { dramratio = 1; }
	}
	if ((mchcfg&3) == 0) { dramratio = 0.75; }


	/* Compute RAM Frequency */
	dramclock = ((extclock /1000) / coef) / dramratio;
	fsb = ((extclock /1000) / coef);

	/* Print DRAM Freq */
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB (only if ECC is not enabled) */
	if ( ctrl.mode == ECC_NONE ) {
		cprint(LINE_CPU+5, col +1, "- FSB : ");
		col += 9;
		dprint(LINE_CPU+5, col, fsb, 3,0);
		col += 3;
		cprint(LINE_CPU+5, col +1, "MHz");
		col += 4;
	}
}

static void poll_fsb_p4(void) {

	ulong fsb, idetect;
	float coef = getP4PMmultiplier();

	fsb = ((extclock /1000) / coef);

	/* Print FSB */
	cprint(LINE_CPU+5, col +1, "/ FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;

	/* For synchro only chipsets */
	pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
	if (idetect == 0x2540 || idetect == 0x254C) {
		print_fsb_info(fsb, "RAM : ", "DDR");
	}
}

static void poll_fsb_i855(void) {


	double dramclock, dramratio, fsb ;
	unsigned int msr_lo, msr_hi;
	ulong mchcfg, centri, idetect;
	int coef;

	pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);

	/* Find multiplier (by MSR) */

	/* Is it a Pentium M ? */
	if (cpu_id.type == 6) {
		rdmsr(0x2A, msr_lo, msr_hi);
		coef = (msr_lo >> 22) & 0x1F;

		/* Is it an i855GM or PM ? */
		if (idetect == 0x3580) {
			cprint(LINE_CPU+5, col-1, "i855GM/GME ");
			col += 10;
		}
	} else {
		rdmsr(0x2C, msr_lo, msr_hi);
		coef = (msr_lo >> 24) & 0x1F;
		cprint(LINE_CPU+5, col-1, "i852PM/GM ");
		col += 9;
	}

	fsb = ((extclock /1000) / coef);

	/* Print FSB */
	cprint(LINE_CPU+5, col, "/ FSB : ");	col += 8;
	dprint(LINE_CPU+5, col, fsb, 3,0);	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");	col += 4;

	/* Is it a Centrino platform or only an i855 platform ? */
	pci_conf_read( 2, 2, 0, 0x02, 2, &centri);
	if (centri == 0x1043) {	cprint(LINE_CPU+5, col +1, "/ Centrino Mobile Platform"); }
	else { cprint(LINE_CPU+5, col +1, "/ Mobile Platform"); }

	/* Compute DRAM Clock */

	dramratio = 1;
	if (idetect == 0x3580) {
		pci_conf_read( 0, 0, 3, 0xC0, 2, &mchcfg);
		mchcfg = mchcfg & 0x7;

		if (mchcfg == 1 || mchcfg == 2 || mchcfg == 4 || mchcfg == 5) {	dramratio = 1; }
		if (mchcfg == 0 || mchcfg == 3) { dramratio = 1.333333333; }
		if (mchcfg == 6) { dramratio = 1.25; }
		if (mchcfg == 7) { dramratio = 1.666666667; }

	} else {
		pci_conf_read( 0, 0, 0, 0xC6, 2, &mchcfg);
		if (((mchcfg >> 10)&3) == 0) { dramratio = 1; }
		else if (((mchcfg >> 10)&3) == 1) { dramratio = 1.666667; }
		else { dramratio = 1.333333333; }
	}


	dramclock = fsb * dramratio;

	/* ...and print */
	print_fsb_info(dramclock, "RAM : ", "DDR");

}

static void poll_fsb_amd32(void) {

	unsigned int mcgsrl;
	unsigned int mcgsth;
	unsigned long temp;
	double dramclock;
	double coef2;

	/* First, got the FID */
	rdmsr(0x0c0010015, mcgsrl, mcgsth);
	temp = (mcgsrl >> 24)&0x0F;

	if ((mcgsrl >> 19)&1) { coef2 = athloncoef2[temp]; }
	else { coef2 = athloncoef[temp]; }

	if (coef2 == 0) { coef2 = 1; };

	/* Compute the final FSB Clock */
	dramclock = (extclock /1000) / coef2;

	/* ...and print */
	print_fsb_info(dramclock, "FSB : ", "DDR");

}

static void poll_fsb_nf2(void) {

	unsigned int mcgsrl;
	unsigned int mcgsth;
	unsigned long temp, mempll;
	double dramclock, fsb;
	double mem_m, mem_n;
	float coef;
	coef = 10;

	/* First, got the FID */
	rdmsr(0x0c0010015, mcgsrl, mcgsth);
	temp = (mcgsrl >> 24)&0x0F;

	if ((mcgsrl >> 19)&1) { coef = athloncoef2[temp]; }
	else { coef = athloncoef[temp]; }

	/* Get the coef (COEF = N/M) - Here is for Crush17 */
	pci_conf_read(0, 0, 3, 0x70, 4, &mempll);
	mem_m = (mempll&0x0F);
	mem_n = ((mempll >> 4) & 0x0F);

	/* If something goes wrong, the chipset is probably a Crush18 */
	if ( mem_m == 0 || mem_n == 0 ) {
		pci_conf_read(0, 0, 3, 0x7C, 4, &mempll);
		mem_m = (mempll&0x0F);
		mem_n = ((mempll >> 4) & 0x0F);
	}

	/* Compute the final FSB Clock */
	dramclock = ((extclock /1000) / coef) * (mem_n/mem_m);
	fsb = ((extclock /1000) / coef);

	/* ...and print */

	cprint(LINE_CPU+5, col, "/ FSB : ");
	col += 8;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");

	print_fsb_info(dramclock, "RAM : ", "DDR");

}

static void poll_fsb_us15w(void) {

	double dramclock, dramratio, fsb, gfx;
	unsigned long msr;

	/* Find dramratio */
	/* D0 MsgRd, 05 Zunit, 03 MSR */
	pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0050300 );		
	pci_conf_read(0, 0, 0, 0xD4, 4, &msr );		
	fsb = ( msr >> 3 ) & 1;

	dramratio = 0.5; 

	// Compute RAM Frequency
	if (( msr >> 3 ) & 1) {
		fsb = 533;
	} else {
		fsb = 400;
	}

	switch (( msr >> 0 ) & 7) {
		case 0:
			gfx = 100;
			break;
		case 1:
			gfx = 133;
			break;
		case 2:
			gfx = 150;
			break;
		case 3:
			gfx = 178;
			break;
		case 4:
			gfx = 200;
			break;
		case 5:
			gfx = 266;
			break;
		default:
			gfx = 0;
			break;
	}	
	
	dramclock = fsb * dramratio;

	// Print DRAM Freq
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB (only if ECC is not enabled) */
	cprint(LINE_CPU+4, col +1, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+4, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+4, col +1, "MHz");
	col += 4;

	cprint(LINE_CPU+4, col +1, "- GFX : ");
	col += 9;
	dprint(LINE_CPU+4, col, gfx, 3,0);
	col += 3;
	cprint(LINE_CPU+4, col +1, "MHz");
	col += 4;

}

static void poll_fsb_nhm(void) {

	double dramclock, dramratio, fsb;
	unsigned long mc_dimm_clk_ratio, qpi_pll_status;
	float coef = getNHMmultiplier();
	float qpi_speed;

	fsb = ((extclock /1000) / coef);

	/* Print FSB */
	cprint(LINE_CPU+5, col +1, "/ FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;
	
	/* Print QPI Speed (if ECC not supported) */
	if(ctrl.mode == ECC_NONE) {
		pci_conf_read(nhm_bus, 2, 1, 0x50, 2, &qpi_pll_status);
		qpi_speed = (qpi_pll_status & 0x7F) * ((extclock / 1000) / coef) * 2;
		cprint(LINE_CPU+5, col +1, "/ QPI : ");
		col += 9;
		dprint(LINE_CPU+5, col, qpi_speed/1000, 1,0);
		col += 1;
		cprint(LINE_CPU+5, col, ".");
		col += 1;		
		qpi_speed = ((qpi_speed / 1000) - (int)(qpi_speed / 1000)) * 10;
		dprint(LINE_CPU+5, col, qpi_speed, 1,0);
		col += 1;		
		cprint(LINE_CPU+5, col +1, "GT/s");
		col += 5;	
	}
	
	/* Get the clock ratio */
	
	pci_conf_read(nhm_bus, 3, 4, 0x54, 2, &mc_dimm_clk_ratio);
	dramratio = (mc_dimm_clk_ratio & 0x1F);
	
	// Compute RAM Frequency
	fsb = ((extclock / 1000) / coef);
	dramclock = fsb * dramratio / 2;

	// Print DRAM Freq
	print_fsb_info(dramclock, "RAM : ", "DDR3-");

}

/* ------------------ Here the code for Timings detection ------------------ */
/* ------------------------------------------------------------------------- */

static void poll_timings_nf4ie(void) {


	ulong regd0, reg8c, reg9c, reg80;
	int cas, rcd, rp, ras;

	cprint(LINE_CPU+5, col +1, "- Type : DDR-II");

	//Now, read Registers
	pci_conf_read( 0, 1, 1, 0xD0, 4, &regd0);
	pci_conf_read( 0, 1, 1, 0x80, 1, &reg80);
	pci_conf_read( 0, 1, 0, 0x8C, 4, &reg8c);
	pci_conf_read( 0, 1, 0, 0x9C, 4, &reg9c);

	// Then, detect timings
	cas = (regd0 >> 4) & 0x7;
	rcd = (reg8c >> 24) & 0xF;
	rp = (reg9c >> 8) & 0xF;
	ras = (reg8c >> 16) & 0x3F;
	
	print_timings_info(cas, rcd, rp, ras);
	
	if (reg80 & 0x3) {
		cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)");
	} else {
		cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)");
	}

}

static void poll_timings_i875(void) {

	ulong dev6, dev62;
	ulong temp;
	float cas;
	int rcd, rp, ras;
	long *ptr, *ptr2;

	/* Read the MMR Base Address & Define the pointer */
	pci_conf_read( 0, 6, 0, 0x10, 4, &dev6);

	/* Now, the PAT ritual ! (Kant and Luciano will love this) */
	pci_conf_read( 0, 6, 0, 0x40, 4, &dev62);
	ptr2=(long*)(dev6+0x68);

	if ((dev62&0x3) == 0 && ((*ptr2 >> 14)&1) == 1) {
		cprint(LINE_CPU+5, col +1, "- PAT : Enabled");
	} else {
		cprint(LINE_CPU+5, col +1, "- PAT : Disabled");
	}

	/* Now, we could check some additionnals timings infos) */

	ptr=(long*)(dev6+0x60);
	// CAS Latency (tCAS)
	temp = ((*ptr >> 5)& 0x3);
	if (temp == 0x0) { cas = 2.5; } else if (temp == 0x1) { cas = 2; } else { cas = 3; }

	// RAS-To-CAS (tRCD)
	temp = ((*ptr >> 2)& 0x3);
	if (temp == 0x0) { rcd = 4; } else if (temp == 0x1) { rcd = 3; } else { rcd = 2; }

	// RAS Precharge (tRP)
	temp = (*ptr&0x3);
	if (temp == 0x0) { rp = 4; } else if (temp == 0x1) { rp = 3; } else { rp = 2; }

	// RAS Active to precharge (tRAS)
	temp = ((*ptr >> 7)& 0x7);
	ras = 10 - temp;

	// Print timings
	print_timings_info(cas, rcd, rp, ras);

	// Print 64 or 128 bits mode
	if (((*ptr2 >> 21)&3) > 0) { 
		cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)");
	} else {
		cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)");
	}
}

static void poll_timings_i925(void) {

	// Thanks for CDH optis
	ulong dev0, drt, drc, dcc, idetect, temp;
	long *ptr;

	//Now, read MMR Base Address
	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
	pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
	dev0 &= 0xFFFFC000;

	//Set pointer for DRT
	ptr=(long*)(dev0+0x114);
	drt = *ptr & 0xFFFFFFFF;

	//Set pointer for DRC
	ptr=(long*)(dev0+0x120);
	drc = *ptr & 0xFFFFFFFF;

	//Set pointer for DCC
	ptr=(long*)(dev0+0x200);
	dcc = *ptr & 0xFFFFFFFF;

	//Determine DDR or DDR-II