controller.c

开源代码

			unsigned long page;

			/* Read the error location */
			pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA4, 4, &uccelog_add);

			/* Parse the error location */
			page = (uccelog_add & 0x7FFFFFFC) >> 2;

			/* Report the error */
			print_ecc_err(page, 0, 0, 0, 0);

			/* Clear Bit */
			pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, ferr & 0x4646);
	}

	/* Check if DRAM_NERR contains data */
	if (nerr & 0x4747) {
			 pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, nerr & 0x4747);
	}
}




/* ------------------ Here the code for FSB detection ------------------ */
/* --------------------------------------------------------------------- */

static float athloncoef[] = {11, 11.5, 12.0, 12.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10.0, 10.5};
static float athloncoef2[] = {12, 19.0, 12.0, 20.0, 13.0, 13.5, 14.0, 21.0, 15.0, 22, 16.0, 16.5, 17.0, 18.0, 23.0, 24.0};
static float p4model1ratios[] = {16, 17, 18, 19, 20, 21, 22, 23, 8, 9, 10, 11, 12, 13, 14, 15};

static float getP4PMmultiplier(void)
{
	unsigned int msr_lo, msr_hi;
	float coef;
	/* Find multiplier (by MSR) */

	if (cpu_id.type == 6) {
		if((cpu_id.feature_flag >> 7) & 1) {
			rdmsr(0x198, msr_lo, msr_hi);
			coef = ((msr_lo >> 8) & 0x1F);
			if ((msr_lo >> 14) & 0x1) { coef = coef + 0.5f; }
		} else {
			rdmsr(0x2A, msr_lo, msr_hi);
			coef = (msr_lo >> 22) & 0x1F;
		}
	}
	else
	{
		if (cpu_id.model < 2)
		{
			rdmsr(0x2A, msr_lo, msr_hi);
			coef = (msr_lo >> 8) & 0xF;
			coef = p4model1ratios[(int)coef];
		}
		else
		{
			rdmsr(0x2C, msr_lo, msr_hi);
			coef = (msr_lo >> 24) & 0x1F;
		}
	}
	return coef;
}

static float getNHMmultiplier(void)
{
	unsigned int msr_lo, msr_hi;
	float coef;
	
	/* Find multiplier (by MSR) */
	/* First, check if Flexible Ratio is Enabled */
	rdmsr(0x194, msr_lo, msr_hi);
	if((msr_lo >> 16) & 1){
		coef = (msr_lo >> 8) & 0xFF;
	 } else {
		rdmsr(0xCE, msr_lo, msr_hi);
		coef = (msr_lo >> 8) & 0xFF;
	 }

	return coef;
}

static void poll_fsb_amd64(void) {

	unsigned int mcgsrl;
	unsigned int mcgsth;
	unsigned long fid, temp2;
	unsigned long dramchr;
	float clockratio;
	double dramclock;

	float coef = 10;

	/* First, got the FID by MSR */
	/* First look if Cool 'n Quiet is supported to choose the best msr */
	if (((cpu_id.pwrcap >> 1) & 1) == 1) {
		rdmsr(0xc0010042, mcgsrl, mcgsth);
		fid = (mcgsrl & 0x3F);
	} else {
		rdmsr(0xc0010015, mcgsrl, mcgsth);
		fid = ((mcgsrl >> 24)& 0x3F);
	}
	
	/* Extreme simplification. */
	coef = ( fid / 2 ) + 4.0;

	/* Support for .5 coef */
	if (fid & 1) { coef = coef + 0.5; }

	/* Next, we need the clock ratio */
	
	if (((cpu_id.ext >> 16) & 0xF) >= 4) {
	/* K8 0FH */
		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
		temp2 = (dramchr & 0x7);
		clockratio = coef;
	
		switch (temp2) {
			case 0x0:
				clockratio = (int)(coef);
				break;
			case 0x1:
				clockratio = (int)(coef * 3.0f/4.0f);
				break;
			case 0x2:
				clockratio = (int)(coef * 3.0f/5.0f);
				break;
			case 0x3:
				clockratio = (int)(coef * 3.0f/6.0f);
				break;
			}	
	
	 } else {
	 /* OLD K8 */
		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
		temp2 = (dramchr >> 20) & 0x7;
		clockratio = coef;
	
		switch (temp2) {
			case 0x0:
				clockratio = (int)(coef * 2.0f);
				break;
			case 0x2:
				clockratio = (int)((coef * 3.0f/2.0f) + 0.81f);
				break;
			case 0x4:
				clockratio = (int)((coef * 4.0f/3.0f) + 0.81f);
				break;
			case 0x5:
				clockratio = (int)((coef * 6.0f/5.0f) + 0.81f);
				break;
			case 0x6:
				clockratio = (int)((coef * 10.0f/9.0f) + 0.81f);
				break;
			case 0x7:
				clockratio = (int)(coef + 0.81f);
				break;
			}
	}

	/* Compute the final DRAM Clock */
	dramclock = (extclock /1000) / clockratio;

	/* ...and print */
	print_fsb_info(dramclock, "RAM : ", "DDR");

}

static void poll_fsb_k10(void) {

	unsigned int mcgsrl;
	unsigned int mcgsth;
	unsigned long temp2;
	unsigned long dramchr;
	unsigned long mainPllId;
	double dramclock;

		/* First, we need the clock ratio */
		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
		temp2 = (dramchr & 0x7);

		switch (temp2) {
			case 0x7: temp2++;
			case 0x6: temp2++;
			case 0x5: temp2++;
			case 0x4: temp2++;
			default:  temp2 += 3;
		}	


	/* Compute the final DRAM Clock */
	if (((cpu_id.ext >> 20) & 0xFF) == 1)
		dramclock = ((temp2 * 200) / 3.0) + 0.25;
	else {
		unsigned long target;
		unsigned long dx;
		unsigned      divisor;


		target = temp2 * 400;

		/* Get the FID by MSR */
		rdmsr(0xc0010071, mcgsrl, mcgsth);

		pci_conf_read(0, 24, 3, 0xD4, 4, &mainPllId);

		if ( mainPllId & 0x40 )
			mainPllId &= 0x3F;
		else
			mainPllId = 8;	/* FID for 1600 */

		mcgsth = (mcgsth >> 17) & 0x3F;
		if ( mcgsth ) {
			if ( mainPllId > mcgsth )
				mainPllId = mcgsth;
		}

		dx = (mainPllId + 8) * 1200;
		for ( divisor = 3; divisor < 100; divisor++ )
			if ( (dx / divisor) <= target )
				break;

		dramclock = ((dx / divisor) / 6.0) + 0.25;
/*
 * 		dramclock = ((((dx * extclock) / divisor) / (mainPllId+8)) / 600000.0) + 0.25;
 */
}

	/* ...and print */
	print_fsb_info(dramclock, "RAM : ", "DDR");

}

static void poll_fsb_i925(void) {

	double dramclock, dramratio, fsb;
	unsigned long mchcfg, mchcfg2, dev0, drc, idetect;
	float coef = getP4PMmultiplier();
	long *ptr;
	
	pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
	
	/* Find dramratio */
	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
	dev0 = dev0 & 0xFFFFC000;
	ptr=(long*)(dev0+0xC00);
	mchcfg = *ptr & 0xFFFF;
	ptr=(long*)(dev0+0x120);
	drc = *ptr & 0xFFFF;
	dramratio = 1;

	mchcfg2 = (mchcfg >> 4)&3;
	
	if ((drc&3) != 2) {
		// We are in DDR1 Mode
		if (mchcfg2 == 1) { dramratio = 0.8; } else { dramratio = 1; }
	} else {
		// We are in DDR2 Mode
		if ((mchcfg >> 2)&1) {
			// We are in FSB1066 Mode
			if (mchcfg2 == 2) { dramratio = 0.75; } else { dramratio = 1; }
		} else {
			switch (mchcfg2) {
				case 1:
					dramratio = 0.66667;
					break;
				case 2:
					if (idetect != 0x2590) { dramratio = 1; } else { dramratio = 1.5; }
					break;
				case 3:
						// Checking for FSB533 Mode & Alviso
						if ((mchcfg & 1) == 0) { dramratio = 1.33334; }
						else if (idetect == 0x2590) { dramratio = 2; }
						else { dramratio = 1.5; }
			}
		}
	}
	// Compute RAM Frequency 
	fsb = ((extclock / 1000) / coef);
	dramclock = fsb * dramratio;

	// Print DRAM Freq 
	print_fsb_info(dramclock, "RAM : ", "DDR"); 
	
	/* Print FSB (only if ECC is not enabled) */
	cprint(LINE_CPU+5, col +1, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;
	
}

static void poll_fsb_i945(void) {

	double dramclock, dramratio, fsb;
	unsigned long mchcfg, dev0;
	float coef = getP4PMmultiplier();
	long *ptr;

	/* Find dramratio */
	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
	dev0 &= 0xFFFFC000;
	ptr=(long*)(dev0+0xC00);
	mchcfg = *ptr & 0xFFFF;
	dramratio = 1;

	switch ((mchcfg >> 4)&7) {
		case 1:	dramratio = 1.0; break;
		case 2:	dramratio = 1.33334; break;
		case 3:	dramratio = 1.66667; break;
		case 4:	dramratio = 2.0; break;
	}

	// Compute RAM Frequency
	fsb = ((extclock / 1000) / coef);
	dramclock = fsb * dramratio;

	// Print DRAM Freq
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB (only if ECC is not enabled) */
	cprint(LINE_CPU+5, col +1, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;

}

static void poll_fsb_i975(void) {

	double dramclock, dramratio, fsb;
	unsigned long mchcfg, dev0, fsb_mch;
	float coef = getP4PMmultiplier();
	long *ptr;

	/* Find dramratio */
	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
	dev0 &= 0xFFFFC000;
	ptr=(long*)(dev0+0xC00);
	mchcfg = *ptr & 0xFFFF;
	dramratio = 1;

	switch (mchcfg & 7) {
		case 1: fsb_mch = 533; break;
		case 2:	fsb_mch = 800; break;
		case 3:	fsb_mch = 667; break;				
		default: fsb_mch = 1066; break;
	}


	switch (fsb_mch) {
	case 533:
		switch ((mchcfg >> 4)&7) {
			case 0:	dramratio = 1.25; break;
			case 1:	dramratio = 1.5; break;
			case 2:	dramratio = 2.0; break;
		}
		break;
		
	default:
	case 800:
		switch ((mchcfg >> 4)&7) {
			case 1:	dramratio = 1.0; break;
			case 2:	dramratio = 1.33334; break;
			case 3:	dramratio = 1.66667; break;
			case 4:	dramratio = 2.0; break;
		}
		break;

	case 1066:
		switch ((mchcfg >> 4)&7) {
			case 1:	dramratio = 0.75; break;
			case 2:	dramratio = 1.0; break;
			case 3:	dramratio = 1.25; break;
			case 4:	dramratio = 1.5; break;
		}
		break;
}


	// Compute RAM Frequency
	fsb = ((extclock / 1000) / coef);
	dramclock = fsb * dramratio;

	// Print DRAM Freq
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB (only if ECC is not enabled) */
	cprint(LINE_CPU+5, col +1, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;

}

static void poll_fsb_i965(void) {

	double dramclock, dramratio, fsb;
	unsigned long mchcfg, dev0, fsb_mch;
	float coef = getP4PMmultiplier();
	long *ptr;

	/* Find dramratio */
	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
	dev0 &= 0xFFFFC000;
	ptr=(long*)(dev0+0xC00);
	mchcfg = *ptr & 0xFFFF;
	dramratio = 1;

	switch (mchcfg & 7) {
		case 0: fsb_mch = 1066; break;
		case 1: fsb_mch = 533; break;
		default: case 2:	fsb_mch = 800; break;
		case 3:	fsb_mch = 667; break;		
		case 4: fsb_mch = 1333; break;
		case 6: fsb_mch = 1600; break;					
	}


	switch (fsb_mch) {
	case 533:
		switch ((mchcfg >> 4)&7) {
			case 1:	dramratio = 2.0; break;
			case 2:	dramratio = 2.5; break;
			case 3:	dramratio = 3.0; break;
		}
		break;
		
	default:
	case 800:
		switch ((mchcfg >> 4)&7) {
			case 0:	dramratio = 1.0; break;
			case 1:	dramratio = 5.0f/4.0f; break;
			case 2:	dramratio = 5.0f/3.0f; break;
			case 3:	dramratio = 2.0; break;
			case 4:	dramratio = 8.0f/3.0f; break;
			case 5:	dramratio = 10.0f/3.0f; break;
		}
		break;

	case 1066:
		switch ((mchcfg >> 4)&7) {
			case 1:	dramratio = 1.0f; break;
			case 2:	dramratio = 5.0f/4.0f; break;
			case 3:	dramratio = 3.0f/2.0f; break;
			case 4:	dramratio = 2.0f; break;
			case 5:	dramratio = 5.0f/2.0f; break;
		}
		break;
	
	case 1333:
		switch ((mchcfg >> 4)&7) {
			case 2:	dramratio = 1.0f; break;
			case 3:	dramratio = 6.0f/5.0f; break;
			case 4:	dramratio = 8.0f/5.0f; break;
			case 5:	dramratio = 2.0f; break;
		}
		break;

	case 1600:
		switch ((mchcfg >> 4)&7) {
			case 3:	dramratio = 1.0f; break;
			case 4:	dramratio = 4.0f/3.0f; break;
			case 5:	dramratio = 3.0f/2.0f; break;
			case 6:	dramratio = 2.0f; break;
		}
		break;

}

	// Compute RAM Frequency
	fsb = ((extclock / 1000) / coef);
	dramclock = fsb * dramratio;

	// Print DRAM Freq
	print_fsb_info(dramclock, "RAM : ", "DDR");

	/* Print FSB (only if ECC is not enabled) */
	cprint(LINE_CPU+5, col +1, "- FSB : ");
	col += 9;
	dprint(LINE_CPU+5, col, fsb, 3,0);
	col += 3;
	cprint(LINE_CPU+5, col +1, "MHz");
	col += 4;

}

static void poll_fsb_im965(void) {

	double dramclock, dramratio, fsb;
	unsigned long mchcfg, dev0, fsb_mch;
	float coef = getP4PMmultiplier();
	long *ptr;

	/* Find dramratio */
	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
	dev0 &= 0xFFFFC000;
	ptr=(long*)(dev0+0xC00);
	mchcfg = *ptr & 0xFFFF;
	dramratio = 1;

	switch (mchcfg & 7) {
		case 1: fsb_mch = 533; break;
		default: case 2:	fsb_mch = 800; break;
		case 3:	fsb_mch = 667; break;				
		case 6:	fsb_mch = 1066; break;			
	}


	switch (fsb_mch) {
	case 533:
		switch ((mchcfg >> 4)&7) {
			case 1:	dramratio = 5.0f/4.0f; break;
			case 2:	dramratio = 3.0f/2.0f; break;
			case 3:	dramratio = 2.0f; break;
		}
		break;

	case 667:
		switch ((mchcfg >> 4)&7) {
			case 1:	dramratio = 1.0f; break;
			case 2:	dramratio = 6.0f/5.0f; break;
			case 3:	dramratio = 8.0f/5.0f; break;
			case 4:	dramratio = 2.0f; break;
			case 5:	dramratio = 12.0f/5.0f; break;
		}
		break;
	default:
	case 800:
		switch ((mchcfg >> 4)&7) {
			case 1:	dramratio = 5.0f/6.0f; break;
			case 2:	dramratio = 1.0f; break;
			case 3:	dramratio = 4.0f/3.0f; break;
			case 4:	dramratio = 5.0f/3.0f; break;
			case 5:	dramratio = 2.0f; break;
		}