init.c

开源代码

				l2_cache = (cpu_id.cache_info[11] << 8);
				l2_cache += cpu_id.cache_info[10];
				break;
			case 2:
			case 4:
				cprint(LINE_CPU, 0, "AMD Athlon (0.18)");
				off = 17;
				l2_cache = (cpu_id.cache_info[11] << 8);
				l2_cache += cpu_id.cache_info[10];
				break;
			case 6:
				l2_cache = (cpu_id.cache_info[11] << 8);
				l2_cache += cpu_id.cache_info[10];
				if (l2_cache == 64) {
					cprint(LINE_CPU, 0, "AMD Duron (0.18)");
				} else {
					cprint(LINE_CPU, 0, "Athlon XP (0.18)");
				}
				off = 16;
				break;
			case 8:
			case 10:
				l2_cache = (cpu_id.cache_info[11] << 8);
				l2_cache += cpu_id.cache_info[10];
				if (l2_cache == 64) {
					cprint(LINE_CPU, 0, "AMD Duron (0.13)");
				} else {
					cprint(LINE_CPU, 0, "Athlon XP (0.13)");
				}
				off = 16;
				break;
			case 3:
			case 7:
				cprint(LINE_CPU, 0, "AMD Duron");
				off = 9;
				/* Duron stepping 0 CPUID for L2 is broken */
				/* (AMD errata T13)*/
				if (cpu_id.step == 0) { /* stepping 0 */
					/* Hard code the right size*/
					l2_cache = 64;
				} else {
					l2_cache = (cpu_id.cache_info[11] << 8);
					l2_cache += cpu_id.cache_info[10];
				}
				break;
			}
			l1_cache = cpu_id.cache_info[3];
			l1_cache += cpu_id.cache_info[7];
			break;
		case 15:
			l1_cache = cpu_id.cache_info[3];
			l2_cache = (cpu_id.cache_info[11] << 8);
			l2_cache += cpu_id.cache_info[10];
			switch(cpu_id.model) {
			default:
				cprint(LINE_CPU, 0, "AMD K8");
				off = 6;
				break;
			case 1:
			case 5:
				if (((cpu_id.ext >> 16) & 0xF) != 0) {
					cprint(LINE_CPU, 0, "AMD Opteron (0.09)");				
				} else {
					cprint(LINE_CPU, 0, "AMD Opteron (0.13)");
				}
				off = 18;
				break;
			case 3:
			case 11:
				cprint(LINE_CPU, 0, "Athlon 64 X2");
				off = 12;				
				break;
			case 8:
				cprint(LINE_CPU, 0, "Turion 64 X2");
				off = 12;						
				break;
			case 4:
			case 7:
			case 9:
			case 12:
			case 14:
			case 15:
				if (((cpu_id.ext >> 16) & 0xF) != 0) {
					if (l2_cache > 256) {
						cprint(LINE_CPU, 0, "Athlon 64 (0.09)");
					} else {
						cprint(LINE_CPU, 0, "Sempron (0.09)");						
					}
				} else {
					if (l2_cache > 256) {
						cprint(LINE_CPU, 0, "Athlon 64 (0.13)");
					} else {
						cprint(LINE_CPU, 0, "Sempron (0.13)");						
					}		
				}
				off = 16;
				break;
			case 2:
				l3_cache = (cpu_id.cache_info[15] << 8);
				l3_cache += (cpu_id.cache_info[14] >> 2);
				l3_cache *= 512;
				cprint(LINE_CPU, 0, "AMD K10 CPU @");
				off = 13;				
				break;				
			}
			break;
		}
		break;

	/* Intel or Transmeta Processors */
	case 'G':
		if ( cpu_id.vend_id[7] == 'T' ) {	/* GenuineTMx86 */
			if (cpu_id.type == 5) {
				cprint(LINE_CPU, 0, "TM 5x00");
				off = 7;
			} else if (cpu_id.type == 15) {
				cprint(LINE_CPU, 0, "TM 8x00");
				off = 7;
			}
			l1_cache = cpu_id.cache_info[3] + cpu_id.cache_info[7];
			l2_cache = (cpu_id.cache_info[11]*256) + cpu_id.cache_info[10];
		} else {				/* GenuineIntel */
			if (cpu_id.type == 4) {
				switch(cpu_id.model) {
				case 0:
				case 1:
					cprint(LINE_CPU, 0, "Intel 486DX");
					off = 11;
					break;
				case 2:
					cprint(LINE_CPU, 0, "Intel 486SX");
					off = 11;
					break;
				case 3:
					cprint(LINE_CPU, 0, "Intel 486DX2");
					off = 12;
					break;
				case 4:
					cprint(LINE_CPU, 0, "Intel 486SL");
					off = 11;
					break;
				case 5:
					cprint(LINE_CPU, 0, "Intel 486SX2");
					off = 12;
					break;
				case 7:
					cprint(LINE_CPU, 0, "Intel 486DX2-WB");
					off = 15;
					break;
				case 8:
					cprint(LINE_CPU, 0, "Intel 486DX4");
					off = 12;
					break;
				case 9:
					cprint(LINE_CPU, 0, "Intel 486DX4-WB");
					off = 15;
					break;
				}
				/* Since we can't get CPU speed or cache info return */
				return;
			}

			/* Get the cache info */
			for (i=0; i<16; i++) {
#ifdef CPUID_DEBUG
				dprint(12,i*3,cpu_id.cache_info[i],2,1);
#endif
				switch(cpu_id.cache_info[i]) {
				case 0x6:
				case 0xa:
				case 0x66:
					l1_cache = 8;
					break;
				case 0x8:
				case 0xc:
				case 0x67:
				case 0x60:
					l1_cache = 16;
					break;
				case 0x9:
				case 0xd:
				case 0x68:
				case 0x2c:
				case 0x30:
					l1_cache = 32;
					break;
				case 0x40:
					l2_cache = 0;
					break;
				case 0x41:
				case 0x79:
				case 0x39:
				case 0x3b:
					l2_cache = 128;
					break;
				case 0x3a:
					l2_cache = 192;
					break;
				case 0x21:
				case 0x42:
				case 0x7a:
				case 0x82:
				case 0x3c:
				case 0x3f:
					l2_cache = 256;
					break;
				case 0x3d:
					l2_cache = 384;
					break;				
				case 0x43:
				case 0x7b:
				case 0x83:
				case 0x86:
				case 0x3e:
				case 0x7f:
				case 0x80:
					l2_cache = 512;
					break;
				case 0x44:
				case 0x7c:
				case 0x84:
				case 0x87:
				case 0x78:
					l2_cache = 1024;
					break;
				case 0x45:
				case 0x7d:
				case 0x85:
					l2_cache = 2048;
					break;
				case 0x48:
					l2_cache = 3072;
					break;
				case 0x49:
					l2_cache = 4096;
					break;
				case 0x4e:
					l2_cache = 6144;
					break;
				case 0xd1:
				case 0xd6:
					l3_cache = 1024;
					break;
				case 0xd2:
				case 0xd7:
				case 0xdc:
				case 0xe2:
					l3_cache = 2048;
					break;
				case 0xd8:
				case 0xdd:
				case 0xe3:
					l3_cache = 4096;
					break;
				case 0xde:
				case 0xe4:
					l3_cache = 8192;
					break;				
				}
			}

			switch(cpu_id.type) {
			case 5:
				switch(cpu_id.model) {
				case 0:
				case 1:
				case 2:
				case 3:
				case 7:
					cprint(LINE_CPU, 0, "Pentium");
					if (l1_cache == 0) {
						l1_cache = 8;
					}
					off = 7;
					break;
				case 4:
				case 8:
					cprint(LINE_CPU, 0, "Pentium-MMX");
					if (l1_cache == 0) {
						l1_cache = 16;
					}
					off = 11;
					break;
				}
				break;
			case 6:
				switch(cpu_id.model) {
				case 0:
				case 1:
					cprint(LINE_CPU, 0, "Pentium Pro");
					off = 11;
					break;
				case 3:
					cprint(LINE_CPU, 0, "Pentium II");
					off = 10;
					break;
				case 5:
				if (((cpu_id.ext >> 16) & 0xF) != 0) {
					cprint(LINE_CPU, 0, "Intel EP80579");
					if (l2_cache == 0) { l2_cache = 256; }
					off = 13;
				} else {
					if (l2_cache == 0) {
						cprint(LINE_CPU, 0, "Celeron");
						off = 7;
					} else {
						cprint(LINE_CPU, 0, "Pentium II");
						off = 10;
					}
				 }
					break;
				case 6:
						if (l2_cache == 128) {
							cprint(LINE_CPU, 0, "Celeron");
							off = 7;
						} else {
							cprint(LINE_CPU, 0, "Pentium II");
							off = 10;
						}
					break;
				case 7:
				case 8:
				case 11:
					if (((cpu_id.ext >> 16) & 0xF) != 0) {
						tsc_invariable = 1;
						if (l2_cache < 1024) {
							cprint(LINE_CPU, 0, "Celeron");
							off = 7;
						} else {
							cprint(LINE_CPU, 0, "Intel Core 2");
							off = 12;
						}					
					} else {
						if (l2_cache == 128) {
							cprint(LINE_CPU, 0, "Celeron");
							off = 7;
						} else {
							cprint(LINE_CPU, 0, "Pentium III");
							off = 11;
						}
					}
					break;
				case 9:
					if (l2_cache == 512) {
						cprint(LINE_CPU, 0, "Celeron M (0.13)");
					} else {
						cprint(LINE_CPU, 0, "Pentium M (0.13)");
					}
					off = 16;
					break;
				case 10:
					if (((cpu_id.ext >> 16) & 0xF) != 0) {
						  tsc_invariable = 1;
							cprint(LINE_CPU, 0, "Intel Core i7");
							off = 13;
						} else {
							cprint(LINE_CPU, 0, "Pentium III Xeon");
							off = 16;
						}					
					break;
				case 12:
					l1_cache = 24;
					cprint(LINE_CPU, 0, "Atom (0.045)");
					off = 12;
					break;					
				case 13:
					if (l2_cache == 1024) {
						cprint(LINE_CPU, 0, "Celeron M (0.09)");
					} else {
						cprint(LINE_CPU, 0, "Pentium M (0.09)");
					}
					off = 16;
					break;
				case 14:
					if (((cpu_id.ext >> 16) & 0xF) != 0) {
						tsc_invariable = 1;
						cprint(LINE_CPU, 0, "Intel Core i5");
						off = 13;
					} else {
						cprint(LINE_CPU, 0, "Intel Core");
						off = 10;
					}
					break;				
				case 15:
					if (l2_cache == 1024) {
						cprint(LINE_CPU, 0, "Pentium E");
						off = 9;
					} else {
						cprint(LINE_CPU, 0, "Intel Core 2");
						off = 12;	
					}				
					tsc_invariable = 1;
					break;
				}
				break;
			case 15:
				switch(cpu_id.model) {
				case 0:
				case 1:
					if (l2_cache == 128) {
						cprint(LINE_CPU, 0, "Celeron (0.18)");
						off = 14;
					} else if (cpu_id.pwrcap == 0x0B) {
						cprint(LINE_CPU, 0, "Xeon DP (0.18)");
						off = 14;
					} else if (cpu_id.pwrcap == 0x0C) {
						cprint(LINE_CPU, 0, "Xeon MP (0.18)");
						off = 14;
					} else {
						cprint(LINE_CPU, 0, "Pentium 4 (0.18)");
						off = 16;
					}
					break;
				case 2:
					if (l2_cache == 128) {
						cprint(LINE_CPU, 0, "Celeron (0.13)");
						off = 14;
					} else if (cpu_id.pwrcap == 0x0B) {
						cprint(LINE_CPU, 0, "Xeon DP (0.13)");
						off = 14;
					} else if (cpu_id.pwrcap == 0x0C) {
						cprint(LINE_CPU, 0, "Xeon MP (0.13)");
						off = 14;
					} else {
						cprint(LINE_CPU, 0, "Pentium 4 (0.13)");
						off = 16;
					}
					break;
				case 3:
				case 4:
					if (l2_cache == 256) {
						cprint(LINE_CPU, 0, "Celeron (0.09)");
						off = 14;
					} else if (cpu_id.pwrcap == 0x0B) {
						cprint(LINE_CPU, 0, "Xeon DP (0.09)");
						off = 14;
					} else if (cpu_id.pwrcap == 0x0C) {
						cprint(LINE_CPU, 0, "Xeon MP (0.09)");
						off = 14;
					} else if ((cpu_id.step == 0x4 || cpu_id.step == 0x7) && cpu_id.model == 0x4) {
						cprint(LINE_CPU, 0, "Pentium D (0.09)");
						off = 16;
					} else {
						cprint(LINE_CPU, 0, "Pentium 4 (0.09)");
						off = 16;
					}
					break;
				case 6:
					cprint(LINE_CPU, 0, "Pentium D (65nm)");
					off = 16;		
					break;
				default:
					cprint(LINE_CPU, 0, "Unknown Intel");
					off = 13;		
					break;													
				}
				break;
			}
		}
		break;