📄 avrnet.lss
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CSPASSIVE;
8c4: c4 98 cbi 0x18, 4 ; 24
// send the contents of the transmit buffer onto the network
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
8c6: 8a e7 ldi r24, 0x7A ; 122
8c8: 8f b9 out 0x0f, r24 ; 15
8ca: 77 99 sbic 0x0e, 7 ; 14
8cc: 09 c0 rjmp .+18 ; 0x8e0 <enc28j60_packet_send+0x60>
8ce: fd cf rjmp .-6 ; 0x8ca <enc28j60_packet_send+0x4a>
// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
if( (enc28j60Read(EIR) & EIR_TXERIF) )
{
8d0: 21 97 sbiw r28, 0x01 ; 1
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
}
8d2: f8 01 movw r30, r16
8d4: 80 81 ld r24, Z
8d6: 8f b9 out 0x0f, r24 ; 15
}
8d8: 77 9b sbis 0x0e, 7 ; 14
8da: fe cf rjmp .-4 ; 0x8d8 <enc28j60_packet_send+0x58>
8dc: 0f 5f subi r16, 0xFF ; 255
8de: 1f 4f sbci r17, 0xFF ; 255
8e0: 20 97 sbiw r28, 0x00 ; 0
8e2: b1 f7 brne .-20 ; 0x8d0 <enc28j60_packet_send+0x50>
//*******************************************************************************************
//
8e4: c4 9a sbi 0x18, 4 ; 24
// Function : enc28j60_mac_is_linked
// Description : return MAC link status.
//
8e6: 48 e0 ldi r20, 0x08 ; 8
8e8: 6f e1 ldi r22, 0x1F ; 31
8ea: 80 e8 ldi r24, 0x80 ; 128
8ec: 0e 94 b7 03 call 0x76e ; 0x76e <enc28j60WriteOp>
//*******************************************************************************************
/*
BYTE enc28j60_mac_is_linked(void)
8f0: 8c e1 ldi r24, 0x1C ; 28
8f2: 0e 94 e6 03 call 0x7cc ; 0x7cc <enc28j60Read>
8f6: 81 ff sbrs r24, 1
8f8: 05 c0 rjmp .+10 ; 0x904 <enc28j60_packet_send+0x84>
{
if ( (enc28j60_read_phyreg(PHSTAT1) & PHSTAT1_LLSTAT ) )
8fa: 48 e0 ldi r20, 0x08 ; 8
8fc: 6f e1 ldi r22, 0x1F ; 31
8fe: 80 ea ldi r24, 0xA0 ; 160
900: 0e 94 b7 03 call 0x76e ; 0x76e <enc28j60WriteOp>
904: df 91 pop r29
906: cf 91 pop r28
908: 1f 91 pop r17
90a: 0f 91 pop r16
90c: 08 95 ret
0000090e <enc28j60_packet_receive>:
return 1;
else
return 0;
}
*/
//*******************************************************************************************
//
// Function : enc28j60_packet_receive
// Description : check received packet and return length of data
//
//*******************************************************************************************
//WORD data_length;
WORD enc28j60_packet_receive ( BYTE *rxtx_buffer, WORD max_length )
{
WORD_BYTES rx_status, data_length;
// check if a packet has been received and buffered
// if( !(enc28j60Read(EIR) & EIR_PKTIF) ){
// The above does not work. See Rev. B4 Silicon Errata point 6.
if( enc28j60Read(EPKTCNT) == 0 )
{
return 0;
}
// Set the read pointer to the start of the received packet
enc28j60Write(ERDPTL, next_packet_ptr.bytes[0]);
90e: bf 92 push r11
910: cf 92 push r12
912: df 92 push r13
914: ef 92 push r14
916: ff 92 push r15
918: 0f 93 push r16
91a: 1f 93 push r17
91c: cf 93 push r28
91e: df 93 push r29
920: 6c 01 movw r12, r24
922: 7b 01 movw r14, r22
enc28j60Write(ERDPTH, next_packet_ptr.bytes[1]);
// read the next packet pointer
next_packet_ptr.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
next_packet_ptr.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
924: 89 e3 ldi r24, 0x39 ; 57
926: 0e 94 e6 03 call 0x7cc ; 0x7cc <enc28j60Read>
92a: 88 23 and r24, r24
92c: 19 f4 brne .+6 ; 0x934 <enc28j60_packet_receive+0x26>
92e: 80 e0 ldi r24, 0x00 ; 0
930: 90 e0 ldi r25, 0x00 ; 0
932: 5a c0 rjmp .+180 ; 0x9e8 <enc28j60_packet_receive+0xda>
// read the packet length (see datasheet page 43)
data_length.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
data_length.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
data_length.word -=4; //remove the CRC count
// read the receive status (see datasheet page 43)
934: 60 91 eb 00 lds r22, 0x00EB
938: 80 e0 ldi r24, 0x00 ; 0
93a: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
rx_status.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
93e: 60 91 ec 00 lds r22, 0x00EC
942: 81 e0 ldi r24, 0x01 ; 1
944: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
rx_status.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
if ( data_length.word > (max_length-1) )
948: 60 e0 ldi r22, 0x00 ; 0
94a: 8a e3 ldi r24, 0x3A ; 58
94c: 0e 94 a4 03 call 0x748 ; 0x748 <enc28j60ReadOp>
950: 80 93 eb 00 sts 0x00EB, r24
{
954: 60 e0 ldi r22, 0x00 ; 0
956: 8a e3 ldi r24, 0x3A ; 58
958: 0e 94 a4 03 call 0x748 ; 0x748 <enc28j60ReadOp>
95c: b8 2e mov r11, r24
95e: 80 93 ec 00 sts 0x00EC, r24
data_length.word = max_length-1;
}
962: 60 e0 ldi r22, 0x00 ; 0
964: 8a e3 ldi r24, 0x3A ; 58
966: 0e 94 a4 03 call 0x748 ; 0x748 <enc28j60ReadOp>
96a: c8 2f mov r28, r24
// check CRC and symbol errors (see datasheet page 44, table 7-3):
96c: 60 e0 ldi r22, 0x00 ; 0
96e: 8a e3 ldi r24, 0x3A ; 58
970: 0e 94 a4 03 call 0x748 ; 0x748 <enc28j60ReadOp>
974: d8 2f mov r29, r24
// The ERXFCON.CRCEN is set by default. Normally we should not
976: 24 97 sbiw r28, 0x04 ; 4
// need to check this.
if ( (rx_status.word & 0x80)==0 )
{
978: 60 e0 ldi r22, 0x00 ; 0
97a: 8a e3 ldi r24, 0x3A ; 58
97c: 0e 94 a4 03 call 0x748 ; 0x748 <enc28j60ReadOp>
980: 08 2f mov r16, r24
// invalid
982: 60 e0 ldi r22, 0x00 ; 0
984: 8a e3 ldi r24, 0x3A ; 58
986: 0e 94 a4 03 call 0x748 ; 0x748 <enc28j60ReadOp>
data_length.word = 0;
}
98a: b7 01 movw r22, r14
98c: 61 50 subi r22, 0x01 ; 1
98e: 70 40 sbci r23, 0x00 ; 0
990: 6c 17 cp r22, r28
992: 7d 07 cpc r23, r29
994: 08 f4 brcc .+2 ; 0x998 <enc28j60_packet_receive+0x8a>
else
{
996: eb 01 movw r28, r22
// read data from rx buffer and save to rxtx_buffer
rx_status.word = data_length.word;
CSACTIVE;
// issue read command
SPDR = ENC28J60_READ_BUF_MEM;
waitspi();
998: 07 fd sbrc r16, 7
99a: 03 c0 rjmp .+6 ; 0x9a2 <enc28j60_packet_receive+0x94>
while(rx_status.word)
{
rx_status.word--;
99c: c0 e0 ldi r28, 0x00 ; 0
99e: d0 e0 ldi r29, 0x00 ; 0
9a0: 14 c0 rjmp .+40 ; 0x9ca <enc28j60_packet_receive+0xbc>
SPDR = 0x00;
waitspi();
*rxtx_buffer++ = SPDR;
}
CSPASSIVE;
9a2: 9e 01 movw r18, r28
}
9a4: c4 98 cbi 0x18, 4 ; 24
// Move the RX read pointer to the start of the next received packet
9a6: 8a e3 ldi r24, 0x3A ; 58
9a8: 8f b9 out 0x0f, r24 ; 15
// This frees the memory we just read out
9aa: 77 99 sbic 0x0e, 7 ; 14
9ac: 0a c0 rjmp .+20 ; 0x9c2 <enc28j60_packet_receive+0xb4>
9ae: fd cf rjmp .-6 ; 0x9aa <enc28j60_packet_receive+0x9c>
enc28j60Write(ERXRDPTL, next_packet_ptr.bytes[0]);
enc28j60Write(ERXRDPTH, next_packet_ptr.bytes[1]);
// decrement the packet counter indicate we are done with this packet
9b0: 1f b8 out 0x0f, r1 ; 15
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
9b2: 77 9b sbis 0x0e, 7 ; 14
9b4: fe cf rjmp .-4 ; 0x9b2 <enc28j60_packet_receive+0xa4>
9b6: 8f b1 in r24, 0x0f ; 15
9b8: f6 01 movw r30, r12
9ba: 81 93 st Z+, r24
9bc: 6f 01 movw r12, r30
9be: 21 50 subi r18, 0x01 ; 1
9c0: 30 40 sbci r19, 0x00 ; 0
9c2: 21 15 cp r18, r1
9c4: 31 05 cpc r19, r1
9c6: a1 f7 brne .-24 ; 0x9b0 <enc28j60_packet_receive+0xa2>
return( data_length.word );
}
9c8: c4 9a sbi 0x18, 4 ; 24
9ca: 60 91 eb 00 lds r22, 0x00EB
9ce: 8c e0 ldi r24, 0x0C ; 12
9d0: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
9d4: 6b 2d mov r22, r11
9d6: 8d e0 ldi r24, 0x0D ; 13
9d8: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
9dc: 40 e4 ldi r20, 0x40 ; 64
9de: 6e e1 ldi r22, 0x1E ; 30
9e0: 80 e8 ldi r24, 0x80 ; 128
9e2: 0e 94 b7 03 call 0x76e ; 0x76e <enc28j60WriteOp>
9e6: ce 01 movw r24, r28
9e8: df 91 pop r29
9ea: cf 91 pop r28
9ec: 1f 91 pop r17
9ee: 0f 91 pop r16
9f0: ff 90 pop r15
9f2: ef 90 pop r14
9f4: df 90 pop r13
9f6: cf 90 pop r12
9f8: bf 90 pop r11
9fa: 08 95 ret
000009fc <enc28j60_init>:
9fc: ef 92 push r14
9fe: ff 92 push r15
a00: 0f 93 push r16
a02: 1f 93 push r17
a04: 7c 01 movw r14, r24
a06: 8b 9a sbi 0x11, 3 ; 17
a08: 8a 98 cbi 0x11, 2 ; 17
a0a: 92 9a sbi 0x12, 2 ; 18
a0c: 93 98 cbi 0x12, 3 ; 18
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a0e: 80 e4 ldi r24, 0x40 ; 64
a10: 9c e9 ldi r25, 0x9C ; 156
a12: 01 97 sbiw r24, 0x01 ; 1
a14: f1 f7 brne .-4 ; 0xa12 <enc28j60_init+0x16>
a16: 93 9a sbi 0x12, 3 ; 18
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a18: 00 e0 ldi r16, 0x00 ; 0
a1a: 10 e0 ldi r17, 0x00 ; 0
a1c: c8 01 movw r24, r16
a1e: 01 97 sbiw r24, 0x01 ; 1
a20: f1 f7 brne .-4 ; 0xa1e <enc28j60_init+0x22>
a22: 87 b3 in r24, 0x17 ; 23
a24: 80 6b ori r24, 0xB0 ; 176
a26: 87 bb out 0x17, r24 ; 23
a28: c4 9a sbi 0x18, 4 ; 24
a2a: 88 b3 in r24, 0x18 ; 24
a2c: 8f 75 andi r24, 0x5F ; 95
a2e: 88 bb out 0x18, r24 ; 24
a30: 80 e5 ldi r24, 0x50 ; 80
a32: 8d b9 out 0x0d, r24 ; 13
a34: 70 9a sbi 0x0e, 0 ; 14
a36: 4f ef ldi r20, 0xFF ; 255
a38: 60 e0 ldi r22, 0x00 ; 0
a3a: 8f ef ldi r24, 0xFF ; 255
a3c: 0e 94 b7 03 call 0x76e ; 0x76e <enc28j60WriteOp>
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a40: c8 01 movw r24, r16
a42: 01 97 sbiw r24, 0x01 ; 1
a44: f1 f7 brne .-4 ; 0xa42 <enc28j60_init+0x46>
a46: 10 92 ec 00 sts 0x00EC, r1
a4a: 10 92 eb 00 sts 0x00EB, r1
a4e: 60 e0 ldi r22, 0x00 ; 0
a50: 88 e0 ldi r24, 0x08 ; 8
a52: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a56: 60 e0 ldi r22, 0x00 ; 0
a58: 89 e0 ldi r24, 0x09 ; 9
a5a: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a5e: 60 e0 ldi r22, 0x00 ; 0
a60: 8c e0 ldi r24, 0x0C ; 12
a62: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a66: 60 e0 ldi r22, 0x00 ; 0
a68: 8d e0 ldi r24, 0x0D ; 13
a6a: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a6e: 63 e2 ldi r22, 0x23 ; 35
a70: 8a e0 ldi r24, 0x0A ; 10
a72: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a76: 6a e1 ldi r22, 0x1A ; 26
a78: 8b e0 ldi r24, 0x0B ; 11
a7a: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a7e: 64 e2 ldi r22, 0x24 ; 36
a80: 84 e0 ldi r24, 0x04 ; 4
a82: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a86: 6a e1 ldi r22, 0x1A ; 26
a88: 85 e0 ldi r24, 0x05 ; 5
a8a: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a8e: 60 e0 ldi r22, 0x00 ; 0
a90: 86 e0 ldi r24, 0x06 ; 6
a92: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a96: 60 e2 ldi r22, 0x20 ; 32
a98: 87 e0 ldi r24, 0x07 ; 7
a9a: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
a9e: 6d e0 ldi r22, 0x0D ; 13
aa0: 80 ec ldi r24, 0xC0 ; 192
aa2: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
aa6: 62 e3 ldi r22, 0x32 ; 50
aa8: 82 ec ldi r24, 0xC2 ; 194
aaa: 0e 94 f1 03 call 0x7e2 ; 0x7e2 <enc28j60Write>
aae: 60 e4 ldi r22, 0x40 ; 64
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