filter.vhd

MATLAB辅助设计数字滤波器源代码

                         coeffs_regs(15);
  coeffs_assigned(16) <= coeffs_in_reg WHEN ( write_address_reg = 1.6000000000000000E+001 ) ELSE
                         coeffs_regs(16);
  coeffs_assigned(17) <= coeffs_in_reg WHEN ( write_address_reg = 1.7000000000000000E+001 ) ELSE
                         coeffs_regs(17);
  coeffs_assigned(18) <= coeffs_in_reg WHEN ( write_address_reg = 1.8000000000000000E+001 ) ELSE
                         coeffs_regs(18);
  coeffs_assigned(19) <= coeffs_in_reg WHEN ( write_address_reg = 1.9000000000000000E+001 ) ELSE
                         coeffs_regs(19);
  coeffs_assigned(20) <= coeffs_in_reg WHEN ( write_address_reg = 2.0000000000000000E+001 ) ELSE
                         coeffs_regs(20);
  coeffs_assigned(21) <= coeffs_in_reg WHEN ( write_address_reg = 2.1000000000000000E+001 ) ELSE
                         coeffs_regs(21);
  coeffs_assigned(22) <= coeffs_in_reg WHEN ( write_address_reg = 2.2000000000000000E+001 ) ELSE
                         coeffs_regs(22);
  coeffs_assigned(23) <= coeffs_in_reg WHEN ( write_address_reg = 2.3000000000000000E+001 ) ELSE
                         coeffs_regs(23);
  coeffs_assigned(24) <= coeffs_in_reg WHEN ( write_address_reg = 2.4000000000000000E+001 ) ELSE
                         coeffs_regs(24);
  coeffs_assigned(25) <= coeffs_in_reg WHEN ( write_address_reg = 2.5000000000000000E+001 ) ELSE
                         coeffs_regs(25);
  coeffs_assigned(26) <= coeffs_in_reg WHEN ( write_address_reg = 2.6000000000000000E+001 ) ELSE
                         coeffs_regs(26);
  coeffs_assigned(27) <= coeffs_in_reg WHEN ( write_address_reg = 2.7000000000000000E+001 ) ELSE
                         coeffs_regs(27);
  coeffs_assigned(28) <= coeffs_in_reg WHEN ( write_address_reg = 2.8000000000000000E+001 ) ELSE
                         coeffs_regs(28);
  coeffs_assigned(29) <= coeffs_in_reg WHEN ( write_address_reg = 2.9000000000000000E+001 ) ELSE
                         coeffs_regs(29);
  coeffs_assigned(30) <= coeffs_in_reg WHEN ( write_address_reg = 3.0000000000000000E+001 ) ELSE
                         coeffs_regs(30);
  coeffs_temp <= coeffs_assigned WHEN ( write_enable_reg = '1' ) ELSE
                 coeffs_regs;
  Coeffs_Registers_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      coeffs_regs <= (OTHERS => 0.0000000000000000E+000);
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        coeffs_regs(0 TO 30) <= coeffs_temp(0 TO 30);
      END IF;
    END IF; 
  END PROCESS Coeffs_Registers_process;

  Coeffs_Shadow_Regs_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      coeffs_shadow <= (OTHERS => 0.0000000000000000E+000);
    ELSIF clk'event AND clk = '1' THEN
      IF write_done_reg = '1' THEN
        coeffs_shadow(0 TO 30) <= coeffs_regs(0 TO 30);
      END IF;
    END IF; 
  END PROCESS Coeffs_Shadow_Regs_process;

  product31 <= delay_pipeline(30) * coeffs_shadow(30);

  product30 <= delay_pipeline(29) * coeffs_shadow(29);

  product29 <= delay_pipeline(28) * coeffs_shadow(28);

  product28 <= delay_pipeline(27) * coeffs_shadow(27);

  product27 <= delay_pipeline(26) * coeffs_shadow(26);

  product26 <= delay_pipeline(25) * coeffs_shadow(25);

  product25 <= delay_pipeline(24) * coeffs_shadow(24);

  product24 <= delay_pipeline(23) * coeffs_shadow(23);

  product23 <= delay_pipeline(22) * coeffs_shadow(22);

  product22 <= delay_pipeline(21) * coeffs_shadow(21);

  product21 <= delay_pipeline(20) * coeffs_shadow(20);

  product20 <= delay_pipeline(19) * coeffs_shadow(19);

  product19 <= delay_pipeline(18) * coeffs_shadow(18);

  product18 <= delay_pipeline(17) * coeffs_shadow(17);

  product17 <= delay_pipeline(16) * coeffs_shadow(16);

  product16 <= delay_pipeline(15) * coeffs_shadow(15);

  product15 <= delay_pipeline(14) * coeffs_shadow(14);

  product14 <= delay_pipeline(13) * coeffs_shadow(13);

  product13 <= delay_pipeline(12) * coeffs_shadow(12);

  product12 <= delay_pipeline(11) * coeffs_shadow(11);

  product11 <= delay_pipeline(10) * coeffs_shadow(10);

  product10 <= delay_pipeline(9) * coeffs_shadow(9);

  product9 <= delay_pipeline(8) * coeffs_shadow(8);

  product8 <= delay_pipeline(7) * coeffs_shadow(7);

  product7 <= delay_pipeline(6) * coeffs_shadow(6);

  product6 <= delay_pipeline(5) * coeffs_shadow(5);

  product5 <= delay_pipeline(4) * coeffs_shadow(4);

  product4 <= delay_pipeline(3) * coeffs_shadow(3);

  product3 <= delay_pipeline(2) * coeffs_shadow(2);

  product2 <= delay_pipeline(1) * coeffs_shadow(1);

  product1 <= delay_pipeline(0) * coeffs_shadow(0);

  sum1_1 <= product31 + product30;

  sum1_2 <= product29 + product28;

  sum1_3 <= product27 + product26;

  sum1_4 <= product25 + product24;

  sum1_5 <= product23 + product22;

  sum1_6 <= product21 + product20;

  sum1_7 <= product19 + product18;

  sum1_8 <= product17 + product16;

  sum1_9 <= product15 + product14;

  sum1_10 <= product13 + product12;

  sum1_11 <= product11 + product10;

  sum1_12 <= product9 + product8;

  sum1_13 <= product7 + product6;

  sum1_14 <= product5 + product4;

  sum1_15 <= product3 + product2;

  sum2_1 <= sum1_1 + sum1_2;

  sum2_2 <= sum1_3 + sum1_4;

  sum2_3 <= sum1_5 + sum1_6;

  sum2_4 <= sum1_7 + sum1_8;

  sum2_5 <= sum1_9 + sum1_10;

  sum2_6 <= sum1_11 + sum1_12;

  sum2_7 <= sum1_13 + sum1_14;

  sum2_8 <= sum1_15 + product1;

  sum3_1 <= sum2_1 + sum2_2;

  sum3_2 <= sum2_3 + sum2_4;

  sum3_3 <= sum2_5 + sum2_6;

  sum3_4 <= sum2_7 + sum2_8;

  sum4_1 <= sum3_1 + sum3_2;

  sum4_2 <= sum3_3 + sum3_4;

  sum5_1 <= sum4_1 + sum4_2;

  Output_Register_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      output_register <= 0.0000000000000000E+000;
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        output_register <= sum5_1;
      END IF;
    END IF; 
  END PROCESS Output_Register_process;

  -- Assignment Statements
  filter_out <= output_register;
END rtl;